1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 15 #include "qemu_private.h" 16 17 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \ 18 bl1_tzram_layout.total_base, \ 19 bl1_tzram_layout.total_size, \ 20 MT_MEMORY | MT_RW | EL3_PAS) 21 22 #define MAP_BL1_RO MAP_REGION_FLAT( \ 23 BL_CODE_BASE, \ 24 BL1_CODE_END - BL_CODE_BASE, \ 25 MT_CODE | EL3_PAS), \ 26 MAP_REGION_FLAT( \ 27 BL1_RO_DATA_BASE, \ 28 BL1_RO_DATA_END \ 29 - BL_RO_DATA_BASE, \ 30 MT_RO_DATA | EL3_PAS) 31 32 #if USE_COHERENT_MEM 33 #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 34 BL_COHERENT_RAM_BASE, \ 35 BL_COHERENT_RAM_END \ 36 - BL_COHERENT_RAM_BASE, \ 37 MT_DEVICE | MT_RW | EL3_PAS) 38 #endif 39 40 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 41 static meminfo_t bl1_tzram_layout; 42 43 44 meminfo_t *bl1_plat_sec_mem_layout(void) 45 { 46 return &bl1_tzram_layout; 47 } 48 49 /******************************************************************************* 50 * Perform any BL1 specific platform actions. 51 ******************************************************************************/ 52 void bl1_early_platform_setup(void) 53 { 54 /* Initialize the console to provide early debug support */ 55 qemu_console_init(); 56 57 /* Allow BL1 to see the whole Trusted RAM */ 58 bl1_tzram_layout.total_base = BL_RAM_BASE; 59 bl1_tzram_layout.total_size = BL_RAM_SIZE; 60 } 61 62 /****************************************************************************** 63 * Perform the very early platform specific architecture setup. This only 64 * does basic initialization. Later architectural setup (bl1_arch_setup()) 65 * does not do anything platform specific. 66 *****************************************************************************/ 67 #ifdef __aarch64__ 68 #define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_el3(__VA_ARGS__) 69 #else 70 #define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__) 71 #endif 72 73 void bl1_plat_arch_setup(void) 74 { 75 const mmap_region_t bl_regions[] = { 76 MAP_BL1_TOTAL, 77 MAP_BL1_RO, 78 #if USE_COHERENT_MEM 79 MAP_BL_COHERENT_RAM, 80 #endif 81 {0} 82 }; 83 84 setup_page_tables(bl_regions, plat_qemu_get_mmap()); 85 #ifdef __aarch64__ 86 enable_mmu_el3(0); 87 #else 88 enable_mmu_svc_mon(0); 89 #endif 90 } 91 92 void bl1_platform_setup(void) 93 { 94 plat_qemu_io_setup(); 95 } 96