1*301d27d9SRadoslaw Biernacki/* 2*301d27d9SRadoslaw Biernacki * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3*301d27d9SRadoslaw Biernacki * 4*301d27d9SRadoslaw Biernacki * SPDX-License-Identifier: BSD-3-Clause 5*301d27d9SRadoslaw Biernacki */ 6*301d27d9SRadoslaw Biernacki 7*301d27d9SRadoslaw Biernacki#include <arch.h> 8*301d27d9SRadoslaw Biernacki#include <asm_macros.S> 9*301d27d9SRadoslaw Biernacki#include <assert_macros.S> 10*301d27d9SRadoslaw Biernacki#include <platform_def.h> 11*301d27d9SRadoslaw Biernacki 12*301d27d9SRadoslaw Biernacki .globl plat_my_core_pos 13*301d27d9SRadoslaw Biernacki .globl plat_get_my_entrypoint 14*301d27d9SRadoslaw Biernacki .globl platform_mem_init 15*301d27d9SRadoslaw Biernacki .globl plat_qemu_calc_core_pos 16*301d27d9SRadoslaw Biernacki .globl plat_crash_console_init 17*301d27d9SRadoslaw Biernacki .globl plat_crash_console_putc 18*301d27d9SRadoslaw Biernacki .globl plat_crash_console_flush 19*301d27d9SRadoslaw Biernacki .globl plat_secondary_cold_boot_setup 20*301d27d9SRadoslaw Biernacki .globl plat_get_my_entrypoint 21*301d27d9SRadoslaw Biernacki .globl plat_is_my_cpu_primary 22*301d27d9SRadoslaw Biernacki 23*301d27d9SRadoslaw Biernackifunc plat_my_core_pos 24*301d27d9SRadoslaw Biernacki mrs x0, mpidr_el1 25*301d27d9SRadoslaw Biernacki b plat_qemu_calc_core_pos 26*301d27d9SRadoslaw Biernackiendfunc plat_my_core_pos 27*301d27d9SRadoslaw Biernacki 28*301d27d9SRadoslaw Biernacki/* 29*301d27d9SRadoslaw Biernacki * unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); 30*301d27d9SRadoslaw Biernacki * With this function: CorePos = (ClusterId * 4) + CoreId 31*301d27d9SRadoslaw Biernacki */ 32*301d27d9SRadoslaw Biernackifunc plat_qemu_calc_core_pos 33*301d27d9SRadoslaw Biernacki and x1, x0, #MPIDR_CPU_MASK 34*301d27d9SRadoslaw Biernacki and x0, x0, #MPIDR_CLUSTER_MASK 35*301d27d9SRadoslaw Biernacki add x0, x1, x0, LSR #6 36*301d27d9SRadoslaw Biernacki ret 37*301d27d9SRadoslaw Biernackiendfunc plat_qemu_calc_core_pos 38*301d27d9SRadoslaw Biernacki 39*301d27d9SRadoslaw Biernacki /* ----------------------------------------------------- 40*301d27d9SRadoslaw Biernacki * unsigned int plat_is_my_cpu_primary (void); 41*301d27d9SRadoslaw Biernacki * 42*301d27d9SRadoslaw Biernacki * Find out whether the current cpu is the primary 43*301d27d9SRadoslaw Biernacki * cpu. 44*301d27d9SRadoslaw Biernacki * ----------------------------------------------------- 45*301d27d9SRadoslaw Biernacki */ 46*301d27d9SRadoslaw Biernackifunc plat_is_my_cpu_primary 47*301d27d9SRadoslaw Biernacki mrs x0, mpidr_el1 48*301d27d9SRadoslaw Biernacki and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 49*301d27d9SRadoslaw Biernacki cmp x0, #QEMU_PRIMARY_CPU 50*301d27d9SRadoslaw Biernacki cset w0, eq 51*301d27d9SRadoslaw Biernacki ret 52*301d27d9SRadoslaw Biernackiendfunc plat_is_my_cpu_primary 53*301d27d9SRadoslaw Biernacki 54*301d27d9SRadoslaw Biernacki /* ----------------------------------------------------- 55*301d27d9SRadoslaw Biernacki * void plat_secondary_cold_boot_setup (void); 56*301d27d9SRadoslaw Biernacki * 57*301d27d9SRadoslaw Biernacki * This function performs any platform specific actions 58*301d27d9SRadoslaw Biernacki * needed for a secondary cpu after a cold reset e.g 59*301d27d9SRadoslaw Biernacki * mark the cpu's presence, mechanism to place it in a 60*301d27d9SRadoslaw Biernacki * holding pen etc. 61*301d27d9SRadoslaw Biernacki * ----------------------------------------------------- 62*301d27d9SRadoslaw Biernacki */ 63*301d27d9SRadoslaw Biernackifunc plat_secondary_cold_boot_setup 64*301d27d9SRadoslaw Biernacki /* Calculate address of our hold entry */ 65*301d27d9SRadoslaw Biernacki bl plat_my_core_pos 66*301d27d9SRadoslaw Biernacki lsl x0, x0, #PLAT_QEMU_HOLD_ENTRY_SHIFT 67*301d27d9SRadoslaw Biernacki mov_imm x2, PLAT_QEMU_HOLD_BASE 68*301d27d9SRadoslaw Biernacki 69*301d27d9SRadoslaw Biernacki /* Wait until we have a go */ 70*301d27d9SRadoslaw Biernackipoll_mailbox: 71*301d27d9SRadoslaw Biernacki ldr x1, [x2, x0] 72*301d27d9SRadoslaw Biernacki cbz x1, 1f 73*301d27d9SRadoslaw Biernacki mov_imm x0, PLAT_QEMU_TRUSTED_MAILBOX_BASE 74*301d27d9SRadoslaw Biernacki ldr x1, [x0] 75*301d27d9SRadoslaw Biernacki br x1 76*301d27d9SRadoslaw Biernacki1: 77*301d27d9SRadoslaw Biernacki wfe 78*301d27d9SRadoslaw Biernacki b poll_mailbox 79*301d27d9SRadoslaw Biernackiendfunc plat_secondary_cold_boot_setup 80*301d27d9SRadoslaw Biernacki 81*301d27d9SRadoslaw Biernackifunc plat_get_my_entrypoint 82*301d27d9SRadoslaw Biernacki /* TODO support warm boot */ 83*301d27d9SRadoslaw Biernacki mov x0, #0 84*301d27d9SRadoslaw Biernacki ret 85*301d27d9SRadoslaw Biernackiendfunc plat_get_my_entrypoint 86*301d27d9SRadoslaw Biernacki 87*301d27d9SRadoslaw Biernackifunc platform_mem_init 88*301d27d9SRadoslaw Biernacki ret 89*301d27d9SRadoslaw Biernackiendfunc platform_mem_init 90*301d27d9SRadoslaw Biernacki 91*301d27d9SRadoslaw Biernacki /* --------------------------------------------- 92*301d27d9SRadoslaw Biernacki * int plat_crash_console_init(void) 93*301d27d9SRadoslaw Biernacki * Function to initialize the crash console 94*301d27d9SRadoslaw Biernacki * without a C Runtime to print crash report. 95*301d27d9SRadoslaw Biernacki * Clobber list : x0, x1, x2 96*301d27d9SRadoslaw Biernacki * --------------------------------------------- 97*301d27d9SRadoslaw Biernacki */ 98*301d27d9SRadoslaw Biernackifunc plat_crash_console_init 99*301d27d9SRadoslaw Biernacki mov_imm x0, PLAT_QEMU_CRASH_UART_BASE 100*301d27d9SRadoslaw Biernacki mov_imm x1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ 101*301d27d9SRadoslaw Biernacki mov_imm x2, PLAT_QEMU_CONSOLE_BAUDRATE 102*301d27d9SRadoslaw Biernacki b console_pl011_core_init 103*301d27d9SRadoslaw Biernackiendfunc plat_crash_console_init 104*301d27d9SRadoslaw Biernacki 105*301d27d9SRadoslaw Biernacki /* --------------------------------------------- 106*301d27d9SRadoslaw Biernacki * int plat_crash_console_putc(int c) 107*301d27d9SRadoslaw Biernacki * Function to print a character on the crash 108*301d27d9SRadoslaw Biernacki * console without a C Runtime. 109*301d27d9SRadoslaw Biernacki * Clobber list : x1, x2 110*301d27d9SRadoslaw Biernacki * --------------------------------------------- 111*301d27d9SRadoslaw Biernacki */ 112*301d27d9SRadoslaw Biernackifunc plat_crash_console_putc 113*301d27d9SRadoslaw Biernacki mov_imm x1, PLAT_QEMU_CRASH_UART_BASE 114*301d27d9SRadoslaw Biernacki b console_pl011_core_putc 115*301d27d9SRadoslaw Biernackiendfunc plat_crash_console_putc 116*301d27d9SRadoslaw Biernacki 117*301d27d9SRadoslaw Biernacki /* --------------------------------------------- 118*301d27d9SRadoslaw Biernacki * int plat_crash_console_flush(int c) 119*301d27d9SRadoslaw Biernacki * Function to force a write of all buffered 120*301d27d9SRadoslaw Biernacki * data that hasn't been output. 121*301d27d9SRadoslaw Biernacki * Out : return -1 on error else return 0. 122*301d27d9SRadoslaw Biernacki * Clobber list : x0, x1 123*301d27d9SRadoslaw Biernacki * --------------------------------------------- 124*301d27d9SRadoslaw Biernacki */ 125*301d27d9SRadoslaw Biernackifunc plat_crash_console_flush 126*301d27d9SRadoslaw Biernacki mov_imm x0, PLAT_QEMU_CRASH_UART_BASE 127*301d27d9SRadoslaw Biernacki b console_pl011_core_flush 128*301d27d9SRadoslaw Biernackiendfunc plat_crash_console_flush 129*301d27d9SRadoslaw Biernacki 130