1*301d27d9SRadoslaw Biernacki/* 2*301d27d9SRadoslaw Biernacki * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3*301d27d9SRadoslaw Biernacki * 4*301d27d9SRadoslaw Biernacki * SPDX-License-Identifier: BSD-3-Clause 5*301d27d9SRadoslaw Biernacki */ 6*301d27d9SRadoslaw Biernacki 7*301d27d9SRadoslaw Biernacki#include <arch.h> 8*301d27d9SRadoslaw Biernacki#include <asm_macros.S> 9*301d27d9SRadoslaw Biernacki#include <assert_macros.S> 10*301d27d9SRadoslaw Biernacki#include <platform_def.h> 11*301d27d9SRadoslaw Biernacki 12*301d27d9SRadoslaw Biernacki .globl plat_my_core_pos 13*301d27d9SRadoslaw Biernacki .globl plat_get_my_entrypoint 14*301d27d9SRadoslaw Biernacki .globl platform_mem_init 15*301d27d9SRadoslaw Biernacki .globl plat_qemu_calc_core_pos 16*301d27d9SRadoslaw Biernacki .globl plat_crash_console_init 17*301d27d9SRadoslaw Biernacki .globl plat_crash_console_putc 18*301d27d9SRadoslaw Biernacki .globl plat_crash_console_flush 19*301d27d9SRadoslaw Biernacki .globl plat_secondary_cold_boot_setup 20*301d27d9SRadoslaw Biernacki .globl plat_get_my_entrypoint 21*301d27d9SRadoslaw Biernacki .globl plat_is_my_cpu_primary 22*301d27d9SRadoslaw Biernacki 23*301d27d9SRadoslaw Biernacki 24*301d27d9SRadoslaw Biernackifunc plat_my_core_pos 25*301d27d9SRadoslaw Biernacki ldcopr r0, MPIDR 26*301d27d9SRadoslaw Biernacki b plat_qemu_calc_core_pos 27*301d27d9SRadoslaw Biernackiendfunc plat_my_core_pos 28*301d27d9SRadoslaw Biernacki 29*301d27d9SRadoslaw Biernacki/* 30*301d27d9SRadoslaw Biernacki * unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); 31*301d27d9SRadoslaw Biernacki * With this function: CorePos = (ClusterId * 4) + CoreId 32*301d27d9SRadoslaw Biernacki */ 33*301d27d9SRadoslaw Biernackifunc plat_qemu_calc_core_pos 34*301d27d9SRadoslaw Biernacki and r1, r0, #MPIDR_CPU_MASK 35*301d27d9SRadoslaw Biernacki and r0, r0, #MPIDR_CLUSTER_MASK 36*301d27d9SRadoslaw Biernacki add r0, r1, r0, LSR #6 37*301d27d9SRadoslaw Biernacki bx lr 38*301d27d9SRadoslaw Biernackiendfunc plat_qemu_calc_core_pos 39*301d27d9SRadoslaw Biernacki 40*301d27d9SRadoslaw Biernacki /* ----------------------------------------------------- 41*301d27d9SRadoslaw Biernacki * unsigned int plat_is_my_cpu_primary (void); 42*301d27d9SRadoslaw Biernacki * 43*301d27d9SRadoslaw Biernacki * Find out whether the current cpu is the primary 44*301d27d9SRadoslaw Biernacki * cpu. 45*301d27d9SRadoslaw Biernacki * ----------------------------------------------------- 46*301d27d9SRadoslaw Biernacki */ 47*301d27d9SRadoslaw Biernackifunc plat_is_my_cpu_primary 48*301d27d9SRadoslaw Biernacki ldcopr r0, MPIDR 49*301d27d9SRadoslaw Biernacki ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 50*301d27d9SRadoslaw Biernacki and r0, r1 51*301d27d9SRadoslaw Biernacki cmp r0, #QEMU_PRIMARY_CPU 52*301d27d9SRadoslaw Biernacki moveq r0, #1 53*301d27d9SRadoslaw Biernacki movne r0, #0 54*301d27d9SRadoslaw Biernacki bx lr 55*301d27d9SRadoslaw Biernackiendfunc plat_is_my_cpu_primary 56*301d27d9SRadoslaw Biernacki 57*301d27d9SRadoslaw Biernacki /* ----------------------------------------------------- 58*301d27d9SRadoslaw Biernacki * void plat_secondary_cold_boot_setup (void); 59*301d27d9SRadoslaw Biernacki * 60*301d27d9SRadoslaw Biernacki * This function performs any platform specific actions 61*301d27d9SRadoslaw Biernacki * needed for a secondary cpu after a cold reset e.g 62*301d27d9SRadoslaw Biernacki * mark the cpu's presence, mechanism to place it in a 63*301d27d9SRadoslaw Biernacki * holding pen etc. 64*301d27d9SRadoslaw Biernacki * ----------------------------------------------------- 65*301d27d9SRadoslaw Biernacki */ 66*301d27d9SRadoslaw Biernackifunc plat_secondary_cold_boot_setup 67*301d27d9SRadoslaw Biernacki /* Calculate address of our hold entry */ 68*301d27d9SRadoslaw Biernacki bl plat_my_core_pos 69*301d27d9SRadoslaw Biernacki lsl r0, r0, #PLAT_QEMU_HOLD_ENTRY_SHIFT 70*301d27d9SRadoslaw Biernacki mov_imm r2, PLAT_QEMU_HOLD_BASE 71*301d27d9SRadoslaw Biernacki 72*301d27d9SRadoslaw Biernacki /* Wait until we have a go */ 73*301d27d9SRadoslaw Biernackipoll_mailbox: 74*301d27d9SRadoslaw Biernacki ldr r1, [r2, r0] 75*301d27d9SRadoslaw Biernacki cmp r1, #0 76*301d27d9SRadoslaw Biernacki beq 1f 77*301d27d9SRadoslaw Biernacki mov_imm r0, PLAT_QEMU_TRUSTED_MAILBOX_BASE 78*301d27d9SRadoslaw Biernacki ldr r1, [r0] 79*301d27d9SRadoslaw Biernacki bx r1 80*301d27d9SRadoslaw Biernacki1: 81*301d27d9SRadoslaw Biernacki wfe 82*301d27d9SRadoslaw Biernacki b poll_mailbox 83*301d27d9SRadoslaw Biernackiendfunc plat_secondary_cold_boot_setup 84*301d27d9SRadoslaw Biernacki 85*301d27d9SRadoslaw Biernackifunc plat_get_my_entrypoint 86*301d27d9SRadoslaw Biernacki /* TODO support warm boot */ 87*301d27d9SRadoslaw Biernacki mov r0, #0 88*301d27d9SRadoslaw Biernacki bx lr 89*301d27d9SRadoslaw Biernackiendfunc plat_get_my_entrypoint 90*301d27d9SRadoslaw Biernacki 91*301d27d9SRadoslaw Biernackifunc platform_mem_init 92*301d27d9SRadoslaw Biernacki bx lr 93*301d27d9SRadoslaw Biernackiendfunc platform_mem_init 94*301d27d9SRadoslaw Biernacki 95*301d27d9SRadoslaw Biernacki /* --------------------------------------------- 96*301d27d9SRadoslaw Biernacki * int plat_crash_console_init(void) 97*301d27d9SRadoslaw Biernacki * Function to initialize the crash console 98*301d27d9SRadoslaw Biernacki * without a C Runtime to print crash report. 99*301d27d9SRadoslaw Biernacki * Clobber list : x0, x1, x2 100*301d27d9SRadoslaw Biernacki * --------------------------------------------- 101*301d27d9SRadoslaw Biernacki */ 102*301d27d9SRadoslaw Biernackifunc plat_crash_console_init 103*301d27d9SRadoslaw Biernacki mov_imm r0, PLAT_QEMU_CRASH_UART_BASE 104*301d27d9SRadoslaw Biernacki mov_imm r1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ 105*301d27d9SRadoslaw Biernacki mov_imm r2, PLAT_QEMU_CONSOLE_BAUDRATE 106*301d27d9SRadoslaw Biernacki b console_pl011_core_init 107*301d27d9SRadoslaw Biernackiendfunc plat_crash_console_init 108*301d27d9SRadoslaw Biernacki 109*301d27d9SRadoslaw Biernacki /* --------------------------------------------- 110*301d27d9SRadoslaw Biernacki * int plat_crash_console_putc(int c) 111*301d27d9SRadoslaw Biernacki * Function to print a character on the crash 112*301d27d9SRadoslaw Biernacki * console without a C Runtime. 113*301d27d9SRadoslaw Biernacki * Clobber list : x1, x2 114*301d27d9SRadoslaw Biernacki * --------------------------------------------- 115*301d27d9SRadoslaw Biernacki */ 116*301d27d9SRadoslaw Biernackifunc plat_crash_console_putc 117*301d27d9SRadoslaw Biernacki mov_imm r1, PLAT_QEMU_CRASH_UART_BASE 118*301d27d9SRadoslaw Biernacki b console_pl011_core_putc 119*301d27d9SRadoslaw Biernackiendfunc plat_crash_console_putc 120*301d27d9SRadoslaw Biernacki 121*301d27d9SRadoslaw Biernacki /* --------------------------------------------- 122*301d27d9SRadoslaw Biernacki * int plat_crash_console_flush(int c) 123*301d27d9SRadoslaw Biernacki * Function to force a write of all buffered 124*301d27d9SRadoslaw Biernacki * data that hasn't been output. 125*301d27d9SRadoslaw Biernacki * Out : return -1 on error else return 0. 126*301d27d9SRadoslaw Biernacki * Clobber list : x0, x1 127*301d27d9SRadoslaw Biernacki * --------------------------------------------- 128*301d27d9SRadoslaw Biernacki */ 129*301d27d9SRadoslaw Biernackifunc plat_crash_console_flush 130*301d27d9SRadoslaw Biernacki mov_imm r0, PLAT_QEMU_CRASH_UART_BASE 131*301d27d9SRadoslaw Biernacki b console_pl011_core_flush 132*301d27d9SRadoslaw Biernackiendfunc plat_crash_console_flush 133*301d27d9SRadoslaw Biernacki 134