xref: /rk3399_ARM-atf/plat/nxp/soc-lx2160a/soc.def (revision 3dbbbca29e3c42a6f9976878f27e1f1fd75b5c8e) 
1#
2# Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
3# Copyright 2017-2020 NXP Semiconductors
4#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7#
8#------------------------------------------------------------------------------
9#
10# This file contains the basic architecture definitions that drive the build
11#
12# -----------------------------------------------------------------------------
13
14CORE_TYPE	:=	a72
15
16CACHE_LINE	:=	6
17
18# set to GIC400 or GIC500
19GIC		:=	GIC500
20
21# set to CCI400 or CCN504 or CCN508
22INTERCONNECT	:=	CCN508
23
24# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
25CHASSIS		:=	3_2
26
27# TZC IP Details TZC used is TZC380 or TZC400
28TZC_ID		:=	TZC400
29
30# CONSOLE Details available is NS16550 or PL011
31CONSOLE		:=	PL011
32
33# Select the DDR PHY generation to be used
34PLAT_DDR_PHY	:=	PHY_GEN2
35
36PHYS_SYS	:=	64
37
38# Area of OCRAM reserved by ROM code
39NXP_ROM_RSVD	:= 0xa000
40
41# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
42# Input to CST create_hdr_esbc tool
43CSF_HDR_SZ	:= 0x3000
44
45NXP_SFP_VER	:= 3_4
46
47# In IMAGE_BL2, compile time flag for handling Cache coherency
48# with CAAM for BL2 running from OCRAM
49SEC_MEM_NON_COHERENT	:= yes
50
51# Defining the endianness for NXP ESDHC
52NXP_ESDHC_ENDIANNESS	:= LE
53
54# Defining the endianness for NXP SFP
55NXP_SFP_ENDIANNESS	:= LE
56
57# Defining the endianness for NXP GPIO
58NXP_GPIO_ENDIANNESS	:= LE
59
60# Defining the endianness for NXP SNVS
61NXP_SNVS_ENDIANNESS	:= LE
62
63# Defining the endianness for NXP CCSR GUR register
64NXP_GUR_ENDIANNESS	:= LE
65
66# Defining the endianness for NXP FSPI register
67NXP_FSPI_ENDIANNESS	:= LE
68
69# Defining the endianness for NXP SEC
70NXP_SEC_ENDIANNESS	:= LE
71
72# Defining the endianness for NXP DDR
73NXP_DDR_ENDIANNESS	:= LE
74
75NXP_DDR_INTLV_256B	:= 1
76
77# OCRAM MAP for BL2
78# Before BL2
79# 0x18000000 - 0x18009fff -> Used by ROM code
80# 0x1800a000 - 0x1800dfff -> CSF header for BL2
81# (The above area i.e 0x18000000 - 0x1800dfff is available
82#  for DDR PHY images scratch pad region during BL2 run time)
83# For FlexSPI boot
84# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary
85# For SD boot
86# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary
87# 0x18030000 - 0x18040000 -> Reserved for SD buffer
88OCRAM_START_ADDR := 0x18000000
89OCRAM_SIZE := 0x40000
90
91# Location of BL2 on OCRAM
92BL2_BASE_ADDR	:=	$(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) )))
93# Covert to HEX to be used by create_pbl.mk
94BL2_BASE	:=	$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc)
95
96# BL2_HDR_LOC is at  (OCRAM_ADDR + NXP_ROM_RSVD)
97# This value BL2_HDR_LOC + CSF_HDR_SZ should not overalp with BL2_BASE
98BL2_HDR_LOC_HDR	?=	$(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) )))
99# Covert to HEX to be used by create_pbl.mk
100BL2_HDR_LOC	:=	$$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc)
101
102# SoC ERRATAS to be enabled
103#
104# Core Errata
105ERRATA_A72_859971	:= 1
106
107# SoC Errata
108ERRATA_SOC_A050426	:= 1
109
110ifneq (${CACHE_LINE},)
111$(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE}))
112$(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE)))))
113$(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE)))
114endif
115
116ifneq (${INTERCONNECT},)
117$(eval $(call add_define,NXP_HAS_CCN508))
118endif
119
120ifneq (${CHASSIS},)
121$(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS}))
122endif
123
124ifneq (${PLAT_DDR_PHY},)
125$(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY}))
126endif
127
128ifneq (${PHYS_SYS},)
129$(eval $(call add_define,CONFIG_PHYS_64BIT))
130endif
131
132ifneq (${CSF_HDR_SZ},)
133$(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ}))
134endif
135
136ifneq (${OCRAM_START_ADDR},)
137$(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR}))
138endif
139
140ifneq (${OCRAM_SIZE},)
141$(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE}))
142endif
143
144ifneq (${NXP_ROM_RSVD},)
145$(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD}))
146endif
147
148ifneq (${BL2_BASE_ADDR},)
149$(eval $(call add_define_val,BL2_BASE,${BL2_BASE_ADDR}))
150endif
151
152ifeq (${SEC_MEM_NON_COHERENT},yes)
153$(eval $(call add_define,SEC_MEM_NON_COHERENT))
154endif
155
156ifneq (${NXP_ESDHC_ENDIANNESS},)
157$(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS}))
158endif
159
160ifneq (${NXP_SFP_VER},)
161$(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER}))
162endif
163
164ifneq (${NXP_SFP_ENDIANNESS},)
165$(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS}))
166endif
167
168ifneq (${NXP_GPIO_ENDIANNESS},)
169$(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS}))
170endif
171
172ifneq (${NXP_SNVS_ENDIANNESS},)
173$(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS}))
174endif
175
176ifneq (${NXP_GUR_ENDIANNESS},)
177$(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS}))
178endif
179
180ifneq (${NXP_FSPI_ENDIANNESS},)
181$(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS}))
182endif
183
184# enable dynamic memory mapping
185PLAT_XLAT_TABLES_DYNAMIC :=	1
186
187ifneq (${NXP_SEC_ENDIANNESS},)
188$(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS}))
189endif
190
191ifneq (${NXP_DDR_ENDIANNESS},)
192$(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS}))
193endif
194
195ifneq (${NXP_DDR_INTLV_256B},)
196$(eval $(call add_define,NXP_DDR_INTLV_256B))
197endif
198
199ifneq (${PLAT_XLAT_TABLES_DYNAMIC},)
200$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
201endif
202