1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #include <assert.h> 9 10 #include <arch.h> 11 #include <bl31/interrupt_mgmt.h> 12 #include <caam.h> 13 #include <cassert.h> 14 #include <ccn.h> 15 #include <common/debug.h> 16 #include <dcfg.h> 17 #ifdef I2C_INIT 18 #include <i2c.h> 19 #endif 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <ls_interconnect.h> 23 #ifdef POLICY_FUSE_PROVISION 24 #include <nxp_gpio.h> 25 #endif 26 #if TRUSTED_BOARD_BOOT 27 #include <nxp_smmu.h> 28 #endif 29 #include <nxp_timer.h> 30 #include <plat_console.h> 31 #include <plat_gic.h> 32 #include <plat_tzc400.h> 33 #include <pmu.h> 34 #if defined(NXP_SFP_ENABLED) 35 #include <sfp.h> 36 #endif 37 38 #include <errata.h> 39 #include <ls_interrupt_mgmt.h> 40 #include "plat_common.h" 41 #ifdef NXP_NV_SW_MAINT_LAST_EXEC_DATA 42 #include <plat_nv_storage.h> 43 #endif 44 #ifdef NXP_WARM_BOOT 45 #include <plat_warm_rst.h> 46 #endif 47 #include "platform_def.h" 48 #include "soc.h" 49 50 static struct soc_type soc_list[] = { 51 SOC_ENTRY(LX2160A, LX2160A, 8, 2), 52 SOC_ENTRY(LX2080A, LX2080A, 8, 1), 53 SOC_ENTRY(LX2120A, LX2120A, 6, 2), 54 }; 55 56 static dcfg_init_info_t dcfg_init_data = { 57 .g_nxp_dcfg_addr = NXP_DCFG_ADDR, 58 .nxp_sysclk_freq = NXP_SYSCLK_FREQ, 59 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ, 60 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, 61 }; 62 static const unsigned char master_to_6rn_id_map[] = { 63 PLAT_6CLUSTER_TO_CCN_ID_MAP 64 }; 65 66 static const unsigned char master_to_rn_id_map[] = { 67 PLAT_CLUSTER_TO_CCN_ID_MAP 68 }; 69 70 CASSERT(ARRAY_SIZE(master_to_rn_id_map) == NUMBER_OF_CLUSTERS, 71 assert_invalid_cluster_count_for_ccn_variant); 72 73 static const ccn_desc_t plat_six_cluster_ccn_desc = { 74 .periphbase = NXP_CCN_ADDR, 75 .num_masters = ARRAY_SIZE(master_to_6rn_id_map), 76 .master_to_rn_id_map = master_to_6rn_id_map 77 }; 78 79 static const ccn_desc_t plat_ccn_desc = { 80 .periphbase = NXP_CCN_ADDR, 81 .num_masters = ARRAY_SIZE(master_to_rn_id_map), 82 .master_to_rn_id_map = master_to_rn_id_map 83 }; 84 85 /****************************************************************************** 86 * Function returns the base counter frequency 87 * after reading the first entry at CNTFID0 (0x20 offset). 88 * 89 * Function is used by: 90 * 1. ARM common code for PSCI management. 91 * 2. ARM Generic Timer init. 92 * 93 *****************************************************************************/ 94 unsigned int plat_get_syscnt_freq2(void) 95 { 96 unsigned int counter_base_frequency; 97 /* 98 * Below register specifies the base frequency of the system counter. 99 * As per NXP Board Manuals: 100 * The system counter always works with SYS_REF_CLK/4 frequency clock. 101 * 102 * 103 */ 104 counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF); 105 106 return counter_base_frequency; 107 } 108 109 #ifdef IMAGE_BL2 110 111 #ifdef POLICY_FUSE_PROVISION 112 static gpio_init_info_t gpio_init_data = { 113 .gpio1_base_addr = NXP_GPIO1_ADDR, 114 .gpio2_base_addr = NXP_GPIO2_ADDR, 115 .gpio3_base_addr = NXP_GPIO3_ADDR, 116 .gpio4_base_addr = NXP_GPIO4_ADDR, 117 }; 118 #endif 119 120 static void soc_interconnect_config(void) 121 { 122 unsigned long long val = 0x0U; 123 uint8_t num_clusters, cores_per_cluster; 124 125 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), 126 &num_clusters, &cores_per_cluster); 127 128 if (num_clusters == 6U) { 129 ccn_init(&plat_six_cluster_ccn_desc); 130 } else { 131 ccn_init(&plat_ccn_desc); 132 } 133 134 /* 135 * Enable Interconnect coherency for the primary CPU's cluster. 136 */ 137 plat_ls_interconnect_enter_coherency(num_clusters); 138 139 val = ccn_read_node_reg(NODE_TYPE_HNI, 13, PCIeRC_RN_I_NODE_ID_OFFSET); 140 val |= (1 << 17); 141 ccn_write_node_reg(NODE_TYPE_HNI, 13, PCIeRC_RN_I_NODE_ID_OFFSET, val); 142 143 /* PCIe is Connected to RN-I 17 which is connected to HN-I 13. */ 144 val = ccn_read_node_reg(NODE_TYPE_HNI, 30, PCIeRC_RN_I_NODE_ID_OFFSET); 145 val |= (1 << 17); 146 ccn_write_node_reg(NODE_TYPE_HNI, 30, PCIeRC_RN_I_NODE_ID_OFFSET, val); 147 148 val = ccn_read_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET); 149 val |= SERIALIZE_DEV_nGnRnE_WRITES; 150 ccn_write_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET, val); 151 152 val = ccn_read_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET); 153 val &= ~(ENABLE_RESERVE_BIT53); 154 val |= SERIALIZE_DEV_nGnRnE_WRITES; 155 ccn_write_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET, val); 156 157 val = ccn_read_node_reg(NODE_TYPE_HNI, 13, PoS_CONTROL_REG_OFFSET); 158 val &= ~(HNI_POS_EN); 159 ccn_write_node_reg(NODE_TYPE_HNI, 13, PoS_CONTROL_REG_OFFSET, val); 160 161 val = ccn_read_node_reg(NODE_TYPE_HNI, 30, PoS_CONTROL_REG_OFFSET); 162 val &= ~(HNI_POS_EN); 163 ccn_write_node_reg(NODE_TYPE_HNI, 30, PoS_CONTROL_REG_OFFSET, val); 164 165 val = ccn_read_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET); 166 val &= ~(POS_EARLY_WR_COMP_EN); 167 ccn_write_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET, val); 168 169 val = ccn_read_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET); 170 val &= ~(POS_EARLY_WR_COMP_EN); 171 ccn_write_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET, val); 172 173 #if POLICY_PERF_WRIOP 174 uint16_t wriop_rni = 0U; 175 176 if (POLICY_PERF_WRIOP == 1) { 177 wriop_rni = 7U; 178 } else if (POLICY_PERF_WRIOP == 2) { 179 wriop_rni = 23U; 180 } else { 181 ERROR("Incorrect WRIOP selected.\n"); 182 panic(); 183 } 184 185 val = ccn_read_node_reg(NODE_TYPE_RNI, wriop_rni, 186 SA_AUX_CTRL_REG_OFFSET); 187 val |= ENABLE_WUO; 188 ccn_write_node_reg(NODE_TYPE_HNI, wriop_rni, SA_AUX_CTRL_REG_OFFSET, 189 val); 190 #else 191 val = ccn_read_node_reg(NODE_TYPE_RNI, 17, SA_AUX_CTRL_REG_OFFSET); 192 val |= ENABLE_WUO; 193 ccn_write_node_reg(NODE_TYPE_RNI, 17, SA_AUX_CTRL_REG_OFFSET, val); 194 #endif 195 } 196 197 198 void soc_preload_setup(void) 199 { 200 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 201 #if defined(NXP_WARM_BOOT) 202 bool warm_reset = is_warm_boot(); 203 #endif 204 info_dram_regions->total_dram_size = 205 #if defined(NXP_WARM_BOOT) 206 init_ddr(warm_reset); 207 #else 208 init_ddr(); 209 #endif 210 } 211 212 /******************************************************************************* 213 * This function implements soc specific erratas 214 * This is called before DDR is initialized or MMU is enabled 215 ******************************************************************************/ 216 void soc_early_init(void) 217 { 218 dcfg_init(&dcfg_init_data); 219 #ifdef POLICY_FUSE_PROVISION 220 gpio_init(&gpio_init_data); 221 sec_init(NXP_CAAM_ADDR); 222 #endif 223 #if LOG_LEVEL > 0 224 /* Initialize the console to provide early debug support */ 225 plat_console_init(NXP_CONSOLE_ADDR, 226 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 227 #endif 228 229 enable_timer_base_to_cluster(NXP_PMU_ADDR); 230 soc_interconnect_config(); 231 232 enum boot_device dev = get_boot_dev(); 233 /* Mark the buffer for SD in OCRAM as non secure. 234 * The buffer is assumed to be at end of OCRAM for 235 * the logic below to calculate TZPC programming 236 */ 237 if (dev == BOOT_DEVICE_EMMC || dev == BOOT_DEVICE_SDHC2_EMMC) { 238 /* Calculate the region in OCRAM which is secure 239 * The buffer for SD needs to be marked non-secure 240 * to allow SD to do DMA operations on it 241 */ 242 uint32_t secure_region = (NXP_OCRAM_SIZE 243 - NXP_SD_BLOCK_BUF_SIZE); 244 uint32_t mask = secure_region/TZPC_BLOCK_SIZE; 245 246 mmio_write_32(NXP_OCRAM_TZPC_ADDR, mask); 247 248 /* Add the entry for buffer in MMU Table */ 249 mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR, 250 NXP_SD_BLOCK_BUF_SIZE, 251 MT_DEVICE | MT_RW | MT_NS); 252 } 253 254 soc_errata(); 255 256 #if (TRUSTED_BOARD_BOOT) || defined(POLICY_FUSE_PROVISION) 257 sfp_init(NXP_SFP_ADDR); 258 #endif 259 260 #if TRUSTED_BOARD_BOOT 261 uint32_t mode; 262 263 /* For secure boot disable SMMU. 264 * Later when platform security policy comes in picture, 265 * this might get modified based on the policy 266 */ 267 if (check_boot_mode_secure(&mode) == true) { 268 bypass_smmu(NXP_SMMU_ADDR); 269 } 270 271 /* For Mbedtls currently crypto is not supported via CAAM 272 * enable it when that support is there. In tbbr.mk 273 * the CAAM_INTEG is set as 0. 274 */ 275 276 #ifndef MBEDTLS_X509 277 /* Initialize the crypto accelerator if enabled */ 278 if (is_sec_enabled() == false) 279 INFO("SEC is disabled.\n"); 280 else 281 sec_init(NXP_CAAM_ADDR); 282 #endif 283 #endif 284 285 /* 286 * Initialize system level generic timer for Layerscape Socs. 287 */ 288 delay_timer_init(NXP_TIMER_ADDR); 289 i2c_init(NXP_I2C_ADDR); 290 } 291 292 void soc_bl2_prepare_exit(void) 293 { 294 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) 295 set_sfp_wr_disable(); 296 #endif 297 } 298 299 /***************************************************************************** 300 * This function returns the boot device based on RCW_SRC 301 ****************************************************************************/ 302 enum boot_device get_boot_dev(void) 303 { 304 enum boot_device src = BOOT_DEVICE_NONE; 305 uint32_t porsr1; 306 uint32_t rcw_src; 307 308 porsr1 = read_reg_porsr1(); 309 310 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; 311 312 switch (rcw_src) { 313 case FLEXSPI_NOR: 314 src = BOOT_DEVICE_FLEXSPI_NOR; 315 INFO("RCW BOOT SRC is FLEXSPI NOR\n"); 316 break; 317 case FLEXSPI_NAND2K_VAL: 318 case FLEXSPI_NAND4K_VAL: 319 INFO("RCW BOOT SRC is FLEXSPI NAND\n"); 320 src = BOOT_DEVICE_FLEXSPI_NAND; 321 break; 322 case SDHC1_VAL: 323 src = BOOT_DEVICE_EMMC; 324 INFO("RCW BOOT SRC is SD\n"); 325 break; 326 case SDHC2_VAL: 327 src = BOOT_DEVICE_SDHC2_EMMC; 328 INFO("RCW BOOT SRC is EMMC\n"); 329 break; 330 default: 331 break; 332 } 333 334 return src; 335 } 336 337 338 void soc_mem_access(void) 339 { 340 const devdisr5_info_t *devdisr5_info = get_devdisr5_info(); 341 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 342 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION]; 343 int dram_idx, index = 0U; 344 345 for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions; 346 dram_idx++) { 347 if (info_dram_regions->region[dram_idx].size == 0) { 348 ERROR("DDR init failure, or"); 349 ERROR("DRAM regions not populated correctly.\n"); 350 break; 351 } 352 353 index = populate_tzc400_reg_list(tzc400_reg_list, 354 dram_idx, index, 355 info_dram_regions->region[dram_idx].addr, 356 info_dram_regions->region[dram_idx].size, 357 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 358 } 359 360 if (devdisr5_info->ddrc1_present != 0) { 361 INFO("DDR Controller 1.\n"); 362 mem_access_setup(NXP_TZC_ADDR, index, 363 tzc400_reg_list); 364 mem_access_setup(NXP_TZC3_ADDR, index, 365 tzc400_reg_list); 366 } 367 if (devdisr5_info->ddrc2_present != 0) { 368 INFO("DDR Controller 2.\n"); 369 mem_access_setup(NXP_TZC2_ADDR, index, 370 tzc400_reg_list); 371 mem_access_setup(NXP_TZC4_ADDR, index, 372 tzc400_reg_list); 373 } 374 } 375 376 #else 377 const unsigned char _power_domain_tree_desc[] = {1, 8, 2, 2, 2, 2, 2, 2, 2, 2}; 378 379 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, 380 assert_invalid_lx2160a_cluster_count); 381 382 /****************************************************************************** 383 * This function returns the SoC topology 384 ****************************************************************************/ 385 386 const unsigned char *plat_get_power_domain_tree_desc(void) 387 { 388 389 return _power_domain_tree_desc; 390 } 391 392 /******************************************************************************* 393 * This function returns the core count within the cluster corresponding to 394 * `mpidr`. 395 ******************************************************************************/ 396 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) 397 { 398 return CORES_PER_CLUSTER; 399 } 400 401 402 void soc_early_platform_setup2(void) 403 { 404 dcfg_init(&dcfg_init_data); 405 /* 406 * Initialize system level generic timer for Socs 407 */ 408 delay_timer_init(NXP_TIMER_ADDR); 409 410 #if LOG_LEVEL > 0 411 /* Initialize the console to provide early debug support */ 412 plat_console_init(NXP_CONSOLE_ADDR, 413 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 414 #endif 415 } 416 417 void soc_platform_setup(void) 418 { 419 /* Initialize the GIC driver, cpu and distributor interfaces */ 420 static uintptr_t target_mask_array[PLATFORM_CORE_COUNT]; 421 static interrupt_prop_t ls_interrupt_props[] = { 422 PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S), 423 PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0) 424 }; 425 426 plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR, 427 PLATFORM_CORE_COUNT, 428 ls_interrupt_props, 429 ARRAY_SIZE(ls_interrupt_props), 430 target_mask_array, 431 plat_core_pos); 432 433 plat_ls_gic_init(); 434 enable_init_timer(); 435 #ifdef LS_SYS_TIMCTL_BASE 436 ls_configure_sys_timer(LS_SYS_TIMCTL_BASE, 437 LS_CONFIG_CNTACR, 438 PLAT_LS_NSTIMER_FRAME_ID); 439 #endif 440 } 441 442 /******************************************************************************* 443 * This function initializes the soc from the BL31 module 444 ******************************************************************************/ 445 void soc_init(void) 446 { 447 uint8_t num_clusters, cores_per_cluster; 448 449 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), 450 &num_clusters, &cores_per_cluster); 451 452 /* low-level init of the soc */ 453 soc_init_start(); 454 soc_init_percpu(); 455 _init_global_data(); 456 _initialize_psci(); 457 458 if (ccn_get_part0_id(NXP_CCN_ADDR) != CCN_508_PART0_ID) { 459 ERROR("Unrecognized CCN variant detected."); 460 ERROR("Only CCN-508 is supported\n"); 461 panic(); 462 } 463 464 if (num_clusters == 6U) { 465 ccn_init(&plat_six_cluster_ccn_desc); 466 } else { 467 ccn_init(&plat_ccn_desc); 468 } 469 470 plat_ls_interconnect_enter_coherency(num_clusters); 471 472 /* Set platform security policies */ 473 _set_platform_security(); 474 475 /* make sure any parallel init tasks are finished */ 476 soc_init_finish(); 477 478 /* Initialize the crypto accelerator if enabled */ 479 if (is_sec_enabled() == false) { 480 INFO("SEC is disabled.\n"); 481 } else { 482 sec_init(NXP_CAAM_ADDR); 483 } 484 485 } 486 487 #ifdef NXP_WDOG_RESTART 488 static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags, 489 void *handle, void *cookie) 490 { 491 uint8_t data = WDOG_RESET_FLAG; 492 493 wr_nv_app_data(WDT_RESET_FLAG_OFFSET, 494 (uint8_t *)&data, sizeof(data)); 495 496 mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT); 497 498 return 0; 499 } 500 #endif 501 502 void soc_runtime_setup(void) 503 { 504 505 #ifdef NXP_WDOG_RESTART 506 request_intr_type_el3(BL31_NS_WDOG_WS1, wdog_interrupt_handler); 507 #endif 508 } 509 #endif 510