1# 2# Copyright 2018-2020 NXP 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# board-specific build parameters 8 9BOOT_MODE ?= flexspi_nor 10BOARD ?= lx2162aqds 11POVDD_ENABLE := no 12NXP_COINED_BB := no 13 14 # DDR Compilation Configs 15NUM_OF_DDRC := 1 16DDRC_NUM_DIMM := 1 17DDRC_NUM_CS := 2 18DDR_ECC_EN := yes 19 #enable address decoding feature 20DDR_ADDR_DEC := yes 21APPLY_MAX_CDD := yes 22 23# DDR Errata 24ERRATA_DDR_A011396 := 1 25ERRATA_DDR_A050450 := 1 26 27 28 # On-Board Flash Details 29FLASH_TYPE := MT35XU512A 30XSPI_FLASH_SZ := 0x10000000 31NXP_XSPI_NOR_UNIT_SIZE := 0x20000 32BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000 33# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This 34# config is enabled for future use cases. 35FSPI_ERASE_4K := 0 36 37 # Platform specific features. 38WARM_BOOT := yes 39 40 # Adding platform specific defines 41 42$(eval $(call add_define_val,BOARD,'"${BOARD}"')) 43 44ifeq (${POVDD_ENABLE},yes) 45$(eval $(call add_define,CONFIG_POVDD_ENABLE)) 46endif 47 48ifneq (${FLASH_TYPE},) 49$(eval $(call add_define,CONFIG_${FLASH_TYPE})) 50endif 51 52ifneq (${XSPI_FLASH_SZ},) 53$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ})) 54endif 55 56ifneq (${FSPI_ERASE_4K},) 57$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K})) 58endif 59 60ifneq (${NUM_OF_DDRC},) 61$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC})) 62endif 63 64ifneq (${DDRC_NUM_DIMM},) 65$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM})) 66endif 67 68ifneq (${DDRC_NUM_CS},) 69$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS})) 70endif 71 72ifeq (${DDR_ADDR_DEC},yes) 73$(eval $(call add_define,CONFIG_DDR_ADDR_DEC)) 74endif 75 76ifeq (${DDR_ECC_EN},yes) 77$(eval $(call add_define,CONFIG_DDR_ECC_EN)) 78endif 79 80# Platform can control the base address for non-volatile storage. 81#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}')) 82 83ifeq (${WARM_BOOT},yes) 84$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}')) 85endif 86 87 # Adding Platform files build files 88BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\ 89 ${BOARD_PATH}/platform.c 90 91 # Adding SoC build info 92include plat/nxp/soc-lx2160a/soc.mk 93