1*1f497308SPankaj Gupta /* 2*1f497308SPankaj Gupta * Copyright 2018-2021 NXP 3*1f497308SPankaj Gupta * 4*1f497308SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*1f497308SPankaj Gupta * 6*1f497308SPankaj Gupta */ 7*1f497308SPankaj Gupta 8*1f497308SPankaj Gupta #ifndef PLAT_DEF_H 9*1f497308SPankaj Gupta #define PLAT_DEF_H 10*1f497308SPankaj Gupta 11*1f497308SPankaj Gupta #include <arch.h> 12*1f497308SPankaj Gupta #include <cortex_a72.h> 13*1f497308SPankaj Gupta /* Required without TBBR. 14*1f497308SPankaj Gupta * To include the defines for DDR PHY 15*1f497308SPankaj Gupta * Images. 16*1f497308SPankaj Gupta */ 17*1f497308SPankaj Gupta #include <tbbr_img_def.h> 18*1f497308SPankaj Gupta 19*1f497308SPankaj Gupta #include <policy.h> 20*1f497308SPankaj Gupta #include <soc.h> 21*1f497308SPankaj Gupta 22*1f497308SPankaj Gupta #if defined(IMAGE_BL31) 23*1f497308SPankaj Gupta #define LS_SYS_TIMCTL_BASE 0x2890000 24*1f497308SPankaj Gupta #define PLAT_LS_NSTIMER_FRAME_ID 0 25*1f497308SPankaj Gupta #define LS_CONFIG_CNTACR 1 26*1f497308SPankaj Gupta #endif 27*1f497308SPankaj Gupta 28*1f497308SPankaj Gupta #define NXP_SYSCLK_FREQ 100000000 29*1f497308SPankaj Gupta #define NXP_DDRCLK_FREQ 100000000 30*1f497308SPankaj Gupta 31*1f497308SPankaj Gupta /* UART related definition */ 32*1f497308SPankaj Gupta #define NXP_CONSOLE_ADDR NXP_UART_ADDR 33*1f497308SPankaj Gupta #define NXP_CONSOLE_BAUDRATE 115200 34*1f497308SPankaj Gupta 35*1f497308SPankaj Gupta /* Size of cacheable stacks */ 36*1f497308SPankaj Gupta #if defined(IMAGE_BL2) 37*1f497308SPankaj Gupta #if defined(TRUSTED_BOARD_BOOT) 38*1f497308SPankaj Gupta #define PLATFORM_STACK_SIZE 0x2000 39*1f497308SPankaj Gupta #else 40*1f497308SPankaj Gupta #define PLATFORM_STACK_SIZE 0x1000 41*1f497308SPankaj Gupta #endif 42*1f497308SPankaj Gupta #elif defined(IMAGE_BL31) 43*1f497308SPankaj Gupta #define PLATFORM_STACK_SIZE 0x1000 44*1f497308SPankaj Gupta #endif 45*1f497308SPankaj Gupta 46*1f497308SPankaj Gupta /* SD block buffer */ 47*1f497308SPankaj Gupta #define NXP_SD_BLOCK_BUF_SIZE (0x8000) 48*1f497308SPankaj Gupta #define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ 49*1f497308SPankaj Gupta - NXP_SD_BLOCK_BUF_SIZE) 50*1f497308SPankaj Gupta 51*1f497308SPankaj Gupta #ifdef SD_BOOT 52*1f497308SPankaj Gupta #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ 53*1f497308SPankaj Gupta - NXP_SD_BLOCK_BUF_SIZE) 54*1f497308SPankaj Gupta #else 55*1f497308SPankaj Gupta #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 56*1f497308SPankaj Gupta #endif 57*1f497308SPankaj Gupta 58*1f497308SPankaj Gupta /* IO defines as needed by IO driver framework */ 59*1f497308SPankaj Gupta #define MAX_IO_DEVICES 4 60*1f497308SPankaj Gupta #define MAX_IO_BLOCK_DEVICES 1 61*1f497308SPankaj Gupta #define MAX_IO_HANDLES 4 62*1f497308SPankaj Gupta 63*1f497308SPankaj Gupta #define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ) 64*1f497308SPankaj Gupta 65*1f497308SPankaj Gupta /* 66*1f497308SPankaj Gupta * FIP image defines - Offset at which FIP Image would be present 67*1f497308SPankaj Gupta * Image would include Bl31 , Bl33 and Bl32 (optional) 68*1f497308SPankaj Gupta */ 69*1f497308SPankaj Gupta #ifdef POLICY_FUSE_PROVISION 70*1f497308SPankaj Gupta #define MAX_FIP_DEVICES 3 71*1f497308SPankaj Gupta #endif 72*1f497308SPankaj Gupta 73*1f497308SPankaj Gupta #ifndef MAX_FIP_DEVICES 74*1f497308SPankaj Gupta #define MAX_FIP_DEVICES 2 75*1f497308SPankaj Gupta #endif 76*1f497308SPankaj Gupta 77*1f497308SPankaj Gupta /* 78*1f497308SPankaj Gupta * ID of the secure physical generic timer interrupt used by the BL32. 79*1f497308SPankaj Gupta */ 80*1f497308SPankaj Gupta #define BL32_IRQ_SEC_PHY_TIMER 29 81*1f497308SPankaj Gupta 82*1f497308SPankaj Gupta #define BL31_WDOG_SEC 89 83*1f497308SPankaj Gupta 84*1f497308SPankaj Gupta #define BL31_NS_WDOG_WS1 108 85*1f497308SPankaj Gupta 86*1f497308SPankaj Gupta /* 87*1f497308SPankaj Gupta * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 88*1f497308SPankaj Gupta * terminology. On a GICv2 system or mode, the lists will be merged and treated 89*1f497308SPankaj Gupta * as Group 0 interrupts. 90*1f497308SPankaj Gupta */ 91*1f497308SPankaj Gupta #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 92*1f497308SPankaj Gupta INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 93*1f497308SPankaj Gupta GIC_INTR_CFG_EDGE) 94*1f497308SPankaj Gupta 95*1f497308SPankaj Gupta /* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ 96*1f497308SPankaj Gupta #define NXP_IRQ_SEC_SGI_7 15 97*1f497308SPankaj Gupta 98*1f497308SPankaj Gupta #define PLAT_LS_G0_IRQ_PROPS(grp) \ 99*1f497308SPankaj Gupta INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 100*1f497308SPankaj Gupta GIC_INTR_CFG_EDGE), \ 101*1f497308SPankaj Gupta INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 102*1f497308SPankaj Gupta GIC_INTR_CFG_EDGE), \ 103*1f497308SPankaj Gupta INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 104*1f497308SPankaj Gupta GIC_INTR_CFG_LEVEL) 105*1f497308SPankaj Gupta #endif 106