1*eb2b193dSPankaj Gupta /* 2*eb2b193dSPankaj Gupta * Copyright 2021 NXP 3*eb2b193dSPankaj Gupta * 4*eb2b193dSPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*eb2b193dSPankaj Gupta * 6*eb2b193dSPankaj Gupta */ 7*eb2b193dSPankaj Gupta 8*eb2b193dSPankaj Gupta #ifndef PLAT_DEF_H 9*eb2b193dSPankaj Gupta #define PLAT_DEF_H 10*eb2b193dSPankaj Gupta 11*eb2b193dSPankaj Gupta #include <arch.h> 12*eb2b193dSPankaj Gupta #include <cortex_a72.h> 13*eb2b193dSPankaj Gupta /* Required without TBBR. 14*eb2b193dSPankaj Gupta * To include the defines for DDR PHY 15*eb2b193dSPankaj Gupta * Images. 16*eb2b193dSPankaj Gupta */ 17*eb2b193dSPankaj Gupta #include <tbbr_img_def.h> 18*eb2b193dSPankaj Gupta 19*eb2b193dSPankaj Gupta #include <policy.h> 20*eb2b193dSPankaj Gupta #include <soc.h> 21*eb2b193dSPankaj Gupta 22*eb2b193dSPankaj Gupta #if defined(IMAGE_BL31) 23*eb2b193dSPankaj Gupta #define LS_SYS_TIMCTL_BASE 0x2890000 24*eb2b193dSPankaj Gupta #define PLAT_LS_NSTIMER_FRAME_ID 0 25*eb2b193dSPankaj Gupta #define LS_CONFIG_CNTACR 1 26*eb2b193dSPankaj Gupta #endif 27*eb2b193dSPankaj Gupta 28*eb2b193dSPankaj Gupta #define NXP_SYSCLK_FREQ 100000000 29*eb2b193dSPankaj Gupta #define NXP_DDRCLK_FREQ 100000000 30*eb2b193dSPankaj Gupta 31*eb2b193dSPankaj Gupta /* UART related definition */ 32*eb2b193dSPankaj Gupta #define NXP_CONSOLE_ADDR NXP_UART_ADDR 33*eb2b193dSPankaj Gupta #define NXP_CONSOLE_BAUDRATE 115200 34*eb2b193dSPankaj Gupta 35*eb2b193dSPankaj Gupta /* Size of cacheable stacks */ 36*eb2b193dSPankaj Gupta #if defined(IMAGE_BL2) 37*eb2b193dSPankaj Gupta #if defined(TRUSTED_BOARD_BOOT) 38*eb2b193dSPankaj Gupta #define PLATFORM_STACK_SIZE 0x2000 39*eb2b193dSPankaj Gupta #else 40*eb2b193dSPankaj Gupta #define PLATFORM_STACK_SIZE 0x1000 41*eb2b193dSPankaj Gupta #endif 42*eb2b193dSPankaj Gupta #elif defined(IMAGE_BL31) 43*eb2b193dSPankaj Gupta #define PLATFORM_STACK_SIZE 0x1000 44*eb2b193dSPankaj Gupta #endif 45*eb2b193dSPankaj Gupta 46*eb2b193dSPankaj Gupta /* SD block buffer */ 47*eb2b193dSPankaj Gupta #define NXP_SD_BLOCK_BUF_SIZE (0x8000) 48*eb2b193dSPankaj Gupta #define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ 49*eb2b193dSPankaj Gupta - NXP_SD_BLOCK_BUF_SIZE) 50*eb2b193dSPankaj Gupta 51*eb2b193dSPankaj Gupta #ifdef SD_BOOT 52*eb2b193dSPankaj Gupta #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ 53*eb2b193dSPankaj Gupta - NXP_SD_BLOCK_BUF_SIZE) 54*eb2b193dSPankaj Gupta #else 55*eb2b193dSPankaj Gupta #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 56*eb2b193dSPankaj Gupta #endif 57*eb2b193dSPankaj Gupta 58*eb2b193dSPankaj Gupta /* IO defines as needed by IO driver framework */ 59*eb2b193dSPankaj Gupta #define MAX_IO_DEVICES 4 60*eb2b193dSPankaj Gupta #define MAX_IO_BLOCK_DEVICES 1 61*eb2b193dSPankaj Gupta #define MAX_IO_HANDLES 4 62*eb2b193dSPankaj Gupta 63*eb2b193dSPankaj Gupta #define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ) 64*eb2b193dSPankaj Gupta 65*eb2b193dSPankaj Gupta /* 66*eb2b193dSPankaj Gupta * FIP image defines - Offset at which FIP Image would be present 67*eb2b193dSPankaj Gupta * Image would include Bl31 , Bl33 and Bl32 (optional) 68*eb2b193dSPankaj Gupta */ 69*eb2b193dSPankaj Gupta #ifdef POLICY_FUSE_PROVISION 70*eb2b193dSPankaj Gupta #define MAX_FIP_DEVICES 3 71*eb2b193dSPankaj Gupta #endif 72*eb2b193dSPankaj Gupta 73*eb2b193dSPankaj Gupta #ifndef MAX_FIP_DEVICES 74*eb2b193dSPankaj Gupta #define MAX_FIP_DEVICES 2 75*eb2b193dSPankaj Gupta #endif 76*eb2b193dSPankaj Gupta 77*eb2b193dSPankaj Gupta /* 78*eb2b193dSPankaj Gupta * ID of the secure physical generic timer interrupt used by the BL32. 79*eb2b193dSPankaj Gupta */ 80*eb2b193dSPankaj Gupta #define BL32_IRQ_SEC_PHY_TIMER 29 81*eb2b193dSPankaj Gupta 82*eb2b193dSPankaj Gupta #define BL31_WDOG_SEC 89 83*eb2b193dSPankaj Gupta 84*eb2b193dSPankaj Gupta #define BL31_NS_WDOG_WS1 108 85*eb2b193dSPankaj Gupta 86*eb2b193dSPankaj Gupta /* 87*eb2b193dSPankaj Gupta * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 88*eb2b193dSPankaj Gupta * terminology. On a GICv2 system or mode, the lists will be merged and treated 89*eb2b193dSPankaj Gupta * as Group 0 interrupts. 90*eb2b193dSPankaj Gupta */ 91*eb2b193dSPankaj Gupta #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 92*eb2b193dSPankaj Gupta INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 93*eb2b193dSPankaj Gupta GIC_INTR_CFG_EDGE) 94*eb2b193dSPankaj Gupta 95*eb2b193dSPankaj Gupta /* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ 96*eb2b193dSPankaj Gupta #define NXP_IRQ_SEC_SGI_7 15 97*eb2b193dSPankaj Gupta 98*eb2b193dSPankaj Gupta #define PLAT_LS_G0_IRQ_PROPS(grp) \ 99*eb2b193dSPankaj Gupta INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 100*eb2b193dSPankaj Gupta GIC_INTR_CFG_EDGE), \ 101*eb2b193dSPankaj Gupta INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 102*eb2b193dSPankaj Gupta GIC_INTR_CFG_EDGE), \ 103*eb2b193dSPankaj Gupta INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 104*eb2b193dSPankaj Gupta GIC_INTR_CFG_LEVEL) 105*eb2b193dSPankaj Gupta #endif 106