1*f359a382SPankaj Gupta /* 2*f359a382SPankaj Gupta * Copyright 2018-2020 NXP 3*f359a382SPankaj Gupta * 4*f359a382SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*f359a382SPankaj Gupta * 6*f359a382SPankaj Gupta */ 7*f359a382SPankaj Gupta 8*f359a382SPankaj Gupta #ifndef PLAT_DEF_H 9*f359a382SPankaj Gupta #define PLAT_DEF_H 10*f359a382SPankaj Gupta 11*f359a382SPankaj Gupta #include <arch.h> 12*f359a382SPankaj Gupta #include <cortex_a72.h> 13*f359a382SPankaj Gupta /* Required without TBBR. 14*f359a382SPankaj Gupta * To include the defines for DDR PHY 15*f359a382SPankaj Gupta * Images. 16*f359a382SPankaj Gupta */ 17*f359a382SPankaj Gupta #include <tbbr_img_def.h> 18*f359a382SPankaj Gupta 19*f359a382SPankaj Gupta #include <policy.h> 20*f359a382SPankaj Gupta #include <soc.h> 21*f359a382SPankaj Gupta 22*f359a382SPankaj Gupta #if defined(IMAGE_BL31) 23*f359a382SPankaj Gupta #define LS_SYS_TIMCTL_BASE 0x2890000 24*f359a382SPankaj Gupta #define PLAT_LS_NSTIMER_FRAME_ID 0 25*f359a382SPankaj Gupta #define LS_CONFIG_CNTACR 1 26*f359a382SPankaj Gupta #endif 27*f359a382SPankaj Gupta 28*f359a382SPankaj Gupta #define NXP_SYSCLK_FREQ 100000000 29*f359a382SPankaj Gupta #define NXP_DDRCLK_FREQ 100000000 30*f359a382SPankaj Gupta 31*f359a382SPankaj Gupta /* UART related definition */ 32*f359a382SPankaj Gupta #define NXP_CONSOLE_ADDR NXP_UART_ADDR 33*f359a382SPankaj Gupta #define NXP_CONSOLE_BAUDRATE 115200 34*f359a382SPankaj Gupta 35*f359a382SPankaj Gupta /* Size of cacheable stacks */ 36*f359a382SPankaj Gupta #if defined(IMAGE_BL2) 37*f359a382SPankaj Gupta #if defined(TRUSTED_BOARD_BOOT) 38*f359a382SPankaj Gupta #define PLATFORM_STACK_SIZE 0x2000 39*f359a382SPankaj Gupta #else 40*f359a382SPankaj Gupta #define PLATFORM_STACK_SIZE 0x1000 41*f359a382SPankaj Gupta #endif 42*f359a382SPankaj Gupta #elif defined(IMAGE_BL31) 43*f359a382SPankaj Gupta #define PLATFORM_STACK_SIZE 0x1000 44*f359a382SPankaj Gupta #endif 45*f359a382SPankaj Gupta 46*f359a382SPankaj Gupta /* SD block buffer */ 47*f359a382SPankaj Gupta #define NXP_SD_BLOCK_BUF_SIZE (0x8000) 48*f359a382SPankaj Gupta #define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ 49*f359a382SPankaj Gupta - NXP_SD_BLOCK_BUF_SIZE) 50*f359a382SPankaj Gupta 51*f359a382SPankaj Gupta #ifdef SD_BOOT 52*f359a382SPankaj Gupta #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ 53*f359a382SPankaj Gupta - NXP_SD_BLOCK_BUF_SIZE) 54*f359a382SPankaj Gupta #else 55*f359a382SPankaj Gupta #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 56*f359a382SPankaj Gupta #endif 57*f359a382SPankaj Gupta 58*f359a382SPankaj Gupta /* IO defines as needed by IO driver framework */ 59*f359a382SPankaj Gupta #define MAX_IO_DEVICES 4 60*f359a382SPankaj Gupta #define MAX_IO_BLOCK_DEVICES 1 61*f359a382SPankaj Gupta #define MAX_IO_HANDLES 4 62*f359a382SPankaj Gupta 63*f359a382SPankaj Gupta #define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ) 64*f359a382SPankaj Gupta 65*f359a382SPankaj Gupta /* 66*f359a382SPankaj Gupta * FIP image defines - Offset at which FIP Image would be present 67*f359a382SPankaj Gupta * Image would include Bl31 , Bl33 and Bl32 (optional) 68*f359a382SPankaj Gupta */ 69*f359a382SPankaj Gupta #ifdef POLICY_FUSE_PROVISION 70*f359a382SPankaj Gupta #define MAX_FIP_DEVICES 3 71*f359a382SPankaj Gupta #endif 72*f359a382SPankaj Gupta 73*f359a382SPankaj Gupta #ifndef MAX_FIP_DEVICES 74*f359a382SPankaj Gupta #define MAX_FIP_DEVICES 2 75*f359a382SPankaj Gupta #endif 76*f359a382SPankaj Gupta 77*f359a382SPankaj Gupta /* 78*f359a382SPankaj Gupta * ID of the secure physical generic timer interrupt used by the BL32. 79*f359a382SPankaj Gupta */ 80*f359a382SPankaj Gupta #define BL32_IRQ_SEC_PHY_TIMER 29 81*f359a382SPankaj Gupta 82*f359a382SPankaj Gupta #define BL31_WDOG_SEC 89 83*f359a382SPankaj Gupta 84*f359a382SPankaj Gupta #define BL31_NS_WDOG_WS1 108 85*f359a382SPankaj Gupta 86*f359a382SPankaj Gupta /* 87*f359a382SPankaj Gupta * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 88*f359a382SPankaj Gupta * terminology. On a GICv2 system or mode, the lists will be merged and treated 89*f359a382SPankaj Gupta * as Group 0 interrupts. 90*f359a382SPankaj Gupta */ 91*f359a382SPankaj Gupta #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 92*f359a382SPankaj Gupta INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 93*f359a382SPankaj Gupta GIC_INTR_CFG_EDGE) 94*f359a382SPankaj Gupta 95*f359a382SPankaj Gupta /* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ 96*f359a382SPankaj Gupta #define NXP_IRQ_SEC_SGI_7 15 97*f359a382SPankaj Gupta 98*f359a382SPankaj Gupta #define PLAT_LS_G0_IRQ_PROPS(grp) \ 99*f359a382SPankaj Gupta INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 100*f359a382SPankaj Gupta GIC_INTR_CFG_EDGE), \ 101*f359a382SPankaj Gupta INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 102*f359a382SPankaj Gupta GIC_INTR_CFG_EDGE), \ 103*f359a382SPankaj Gupta INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 104*f359a382SPankaj Gupta GIC_INTR_CFG_LEVEL) 105*f359a382SPankaj Gupta #endif 106