1 /* 2 * Copyright 2018-2020 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <stdio.h> 13 #include <stdlib.h> 14 #include <string.h> 15 16 #include <common/debug.h> 17 #include <ddr.h> 18 #include <lib/utils.h> 19 #include <load_img.h> 20 21 #include "plat_common.h" 22 #include <platform_def.h> 23 24 #ifdef CONFIG_STATIC_DDR 25 26 const struct ddr_cfg_regs static_3200 = { 27 .cs[0].bnds = U(0x03FF), 28 .cs[1].bnds = U(0x03FF), 29 .cs[0].config = U(0x80050422), 30 .cs[1].config = U(0x80000422), 31 .cs[2].bnds = U(0x00), 32 .cs[3].bnds = U(0x00), 33 .cs[2].config = U(0x00), 34 .cs[3].config = U(0x00), 35 .timing_cfg[0] = U(0xFFAA0018), 36 .timing_cfg[1] = U(0x646A8844), 37 .timing_cfg[2] = U(0x00058022), 38 .timing_cfg[3] = U(0x13622100), 39 .timing_cfg[4] = U(0x02), 40 .timing_cfg[5] = U(0x07401400), 41 .timing_cfg[7] = U(0x3BB00000), 42 .timing_cfg[8] = U(0x0944AC00), 43 .sdram_cfg[0] = U(0x65044008), 44 .sdram_cfg[1] = U(0x00401011), 45 .sdram_cfg[2] = U(0x00), 46 .sdram_mode[0] = U(0x06010C50), 47 .sdram_mode[1] = U(0x00280400), 48 .sdram_mode[2] = U(0x00), 49 .sdram_mode[3] = U(0x00), 50 .sdram_mode[4] = U(0x00), 51 .sdram_mode[5] = U(0x00), 52 .sdram_mode[6] = U(0x00), 53 .sdram_mode[7] = U(0x00), 54 .sdram_mode[8] = U(0x0500), 55 .sdram_mode[9] = U(0x10240000), 56 .sdram_mode[10] = U(0x00), 57 .sdram_mode[11] = U(0x00), 58 .sdram_mode[12] = U(0x00), 59 .sdram_mode[13] = U(0x00), 60 .sdram_mode[14] = U(0x00), 61 .sdram_mode[15] = U(0x00), 62 .md_cntl = U(0x00), 63 .interval = U(0x30C00000), 64 .data_init = U(0xDEADBEEF), 65 .init_addr = U(0x00), 66 .zq_cntl = U(0x8A090705), 67 .sdram_rcw[0] = U(0x00), 68 .sdram_rcw[1] = U(0x00), 69 .sdram_rcw[2] = U(0x00), 70 .sdram_rcw[3] = U(0x00), 71 .sdram_rcw[4] = U(0x00), 72 .sdram_rcw[5] = U(0x00), 73 .err_disable = U(0x00), 74 .err_int_en = U(0x00), 75 }; 76 77 const struct ddr_cfg_regs static_2900 = { 78 .cs[0].bnds = U(0x03FF), 79 .cs[1].bnds = U(0x03FF), 80 .cs[0].config = U(0x80050422), 81 .cs[1].config = U(0x80000422), 82 .cs[2].bnds = U(0x00), 83 .cs[3].bnds = U(0x00), 84 .cs[2].config = U(0x00), 85 .cs[3].config = U(0x00), 86 .timing_cfg[0] = U(0xFF990018), 87 .timing_cfg[1] = U(0x4F4A4844), 88 .timing_cfg[2] = U(0x0005601F), 89 .timing_cfg[3] = U(0x125F2100), 90 .timing_cfg[4] = U(0x02), 91 .timing_cfg[5] = U(0x07401400), 92 .timing_cfg[7] = U(0x3AA00000), 93 .timing_cfg[8] = U(0x09449B00), 94 .sdram_cfg[0] = U(0x65044008), 95 .sdram_cfg[1] = U(0x00401011), 96 .sdram_cfg[2] = U(0x00), 97 .sdram_mode[0] = U(0x06010C50), 98 .sdram_mode[1] = U(0x00280400), 99 .sdram_mode[2] = U(0x00), 100 .sdram_mode[3] = U(0x00), 101 .sdram_mode[4] = U(0x00), 102 .sdram_mode[5] = U(0x00), 103 .sdram_mode[6] = U(0x00), 104 .sdram_mode[7] = U(0x00), 105 .sdram_mode[8] = U(0x0500), 106 .sdram_mode[9] = U(0x10240000), 107 .sdram_mode[10] = U(0x00), 108 .sdram_mode[11] = U(0x00), 109 .sdram_mode[12] = U(0x00), 110 .sdram_mode[13] = U(0x00), 111 .sdram_mode[14] = U(0x00), 112 .sdram_mode[15] = U(0x00), 113 .md_cntl = U(0x00), 114 .interval = U(0x2C2E0000), 115 .data_init = U(0xDEADBEEF), 116 .init_addr = U(0x00), 117 .zq_cntl = U(0x8A090705), 118 .sdram_rcw[0] = U(0x00), 119 .sdram_rcw[1] = U(0x00), 120 .sdram_rcw[2] = U(0x00), 121 .sdram_rcw[3] = U(0x00), 122 .sdram_rcw[4] = U(0x00), 123 .sdram_rcw[5] = U(0x00), 124 .err_disable = U(0x00), 125 .err_int_en = U(0x00), 126 }; 127 128 const struct ddr_cfg_regs static_2600 = { 129 .cs[0].bnds = U(0x03FF), 130 .cs[1].bnds = U(0x03FF), 131 .cs[0].config = U(0x80050422), 132 .cs[1].config = U(0x80000422), 133 .cs[2].bnds = U(0x00), 134 .cs[3].bnds = U(0x00), 135 .cs[2].config = U(0x00), 136 .cs[3].config = U(0x00), 137 .timing_cfg[0] = U(0xFF880018), 138 .timing_cfg[1] = U(0x2A24F444), 139 .timing_cfg[2] = U(0x007141DC), 140 .timing_cfg[3] = U(0x125B2100), 141 .timing_cfg[4] = U(0x02), 142 .timing_cfg[5] = U(0x06401400), 143 .timing_cfg[7] = U(0x28800000), 144 .timing_cfg[8] = U(0x07338A00), 145 .sdram_cfg[0] = U(0x65044008), 146 .sdram_cfg[1] = U(0x00401011), 147 .sdram_cfg[2] = U(0x00), 148 .sdram_mode[0] = U(0x06010A70), 149 .sdram_mode[1] = U(0x00200400), 150 .sdram_mode[2] = U(0x00), 151 .sdram_mode[3] = U(0x00), 152 .sdram_mode[4] = U(0x00), 153 .sdram_mode[5] = U(0x00), 154 .sdram_mode[6] = U(0x00), 155 .sdram_mode[7] = U(0x00), 156 .sdram_mode[8] = U(0x0500), 157 .sdram_mode[9] = U(0x0C240000), 158 .sdram_mode[10] = U(0x00), 159 .sdram_mode[11] = U(0x00), 160 .sdram_mode[12] = U(0x00), 161 .sdram_mode[13] = U(0x00), 162 .sdram_mode[14] = U(0x00), 163 .sdram_mode[15] = U(0x00), 164 .md_cntl = U(0x00), 165 .interval = U(0x279C0000), 166 .data_init = U(0xDEADBEEF), 167 .init_addr = U(0x00), 168 .zq_cntl = U(0x8A090705), 169 .sdram_rcw[0] = U(0x00), 170 .sdram_rcw[1] = U(0x00), 171 .sdram_rcw[2] = U(0x00), 172 .sdram_rcw[3] = U(0x00), 173 .sdram_rcw[4] = U(0x00), 174 .sdram_rcw[5] = U(0x00), 175 .err_disable = U(0x00), 176 .err_int_en = U(0x00), 177 }; 178 179 const struct dimm_params static_dimm = { 180 .rdimm = U(0), 181 .primary_sdram_width = U(64), 182 .ec_sdram_width = U(8), 183 .n_ranks = U(2), 184 .device_width = U(8), 185 .mirrored_dimm = U(1), 186 }; 187 188 /* Sample code using two UDIMM MT18ASF1G72AZ-2G6B1, on each DDR controller */ 189 unsigned long long board_static_ddr(struct ddr_info *priv) 190 { 191 (void)memcpy(&priv->ddr_reg, &static_2900, sizeof(static_2900)); 192 (void)memcpy(&priv->dimm, &static_dimm, sizeof(static_dimm)); 193 priv->conf.cs_on_dimm[0] = 0x3; 194 ddr_board_options(priv); 195 compute_ddr_phy(priv); 196 197 return ULL(0x400000000); 198 } 199 200 #elif defined(CONFIG_DDR_NODIMM) 201 /* 202 * Sample code to bypass reading SPD. This is a sample, not recommended 203 * for boards with slots. DDR model number: UDIMM MT18ASF1G72AZ-2G6B1. 204 */ 205 206 const struct dimm_params ddr_raw_timing = { 207 .n_ranks = U(2), 208 .rank_density = U(4294967296u), 209 .capacity = U(8589934592u), 210 .primary_sdram_width = U(64), 211 .ec_sdram_width = U(8), 212 .device_width = U(8), 213 .die_density = U(0x4), 214 .rdimm = U(0), 215 .mirrored_dimm = U(1), 216 .n_row_addr = U(15), 217 .n_col_addr = U(10), 218 .bank_addr_bits = U(0), 219 .bank_group_bits = U(2), 220 .edc_config = U(2), 221 .burst_lengths_bitmask = U(0x0c), 222 .tckmin_x_ps = 750, 223 .tckmax_ps = 1600, 224 .caslat_x = U(0x00FFFC00), 225 .taa_ps = 13750, 226 .trcd_ps = 13750, 227 .trp_ps = 13750, 228 .tras_ps = 32000, 229 .trc_ps = 457500, 230 .twr_ps = 15000, 231 .trfc1_ps = 260000, 232 .trfc2_ps = 160000, 233 .trfc4_ps = 110000, 234 .tfaw_ps = 21000, 235 .trrds_ps = 3000, 236 .trrdl_ps = 4900, 237 .tccdl_ps = 5000, 238 .refresh_rate_ps = U(7800000), 239 }; 240 241 int ddr_get_ddr_params(struct dimm_params *pdimm, 242 struct ddr_conf *conf) 243 { 244 static const char dimm_model[] = "Fixed DDR on board"; 245 246 conf->dimm_in_use[0] = 1; /* Modify accordingly */ 247 memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params)); 248 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 249 250 /* valid DIMM mask, change accordingly, together with dimm_on_ctlr. */ 251 return 0x5; 252 } 253 #endif /* CONFIG_DDR_NODIMM */ 254 255 int ddr_board_options(struct ddr_info *priv) 256 { 257 struct memctl_opt *popts = &priv->opt; 258 const struct ddr_conf *conf = &priv->conf; 259 260 popts->vref_dimm = U(0x24); /* range 1, 83.4% */ 261 popts->rtt_override = 0; 262 popts->rtt_park = U(240); 263 popts->otf_burst_chop_en = 0; 264 popts->burst_length = U(DDR_BL8); 265 popts->trwt_override = U(1); 266 popts->bstopre = U(0); /* auto precharge */ 267 popts->addr_hash = 1; 268 269 /* Set ODT impedance on PHY side */ 270 switch (conf->cs_on_dimm[1]) { 271 case 0xc: /* Two slots dual rank */ 272 case 0x4: /* Two slots single rank, not valid for interleaving */ 273 popts->trwt = U(0xf); 274 popts->twrt = U(0x7); 275 popts->trrt = U(0x7); 276 popts->twwt = U(0x7); 277 popts->vref_phy = U(0x6B); /* 83.6% */ 278 popts->odt = U(60); 279 popts->phy_tx_impedance = U(28); 280 break; 281 case 0: /* One slot used */ 282 default: 283 popts->trwt = U(0x3); 284 popts->twrt = U(0x3); 285 popts->trrt = U(0x3); 286 popts->twwt = U(0x3); 287 popts->vref_phy = U(0x60); /* 75% */ 288 popts->odt = U(48); 289 popts->phy_tx_impedance = U(28); 290 break; 291 } 292 293 return 0; 294 } 295 296 #ifdef NXP_WARM_BOOT 297 long long init_ddr(uint32_t wrm_bt_flg) 298 #else 299 long long init_ddr(void) 300 #endif 301 { 302 int spd_addr[] = {0x51U, 0x52U, 0x53U, 0x54U}; 303 struct ddr_info info; 304 struct sysinfo sys; 305 long long dram_size; 306 307 zeromem(&sys, sizeof(sys)); 308 if (get_clocks(&sys) == 1) { 309 ERROR("System clocks are not set.\n"); 310 panic(); 311 } 312 debug("platform clock %lu\n", sys.freq_platform); 313 debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0); 314 debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1); 315 316 zeromem(&info, sizeof(info)); 317 318 /* Set two DDRC. Unused DDRC will be removed automatically. */ 319 info.num_ctlrs = NUM_OF_DDRC; 320 info.spd_addr = spd_addr; 321 info.ddr[0] = (void *)NXP_DDR_ADDR; 322 info.ddr[1] = (void *)NXP_DDR2_ADDR; 323 info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; 324 info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; 325 info.clk = get_ddr_freq(&sys, 0); 326 info.img_loadr = load_img; 327 info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER; 328 if (info.clk == 0) { 329 info.clk = get_ddr_freq(&sys, 1); 330 } 331 info.dimm_on_ctlr = DDRC_NUM_DIMM; 332 333 info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED; 334 #ifdef NXP_WARM_BOOT 335 info.warm_boot_flag = DDR_COLD_BOOT; 336 if (wrm_bt_flg != 0U) { 337 info.warm_boot_flag = DDR_WARM_BOOT; 338 } else { 339 info.warm_boot_flag = DDR_COLD_BOOT; 340 } 341 #endif 342 343 dram_size = dram_init(&info 344 #if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508) 345 , NXP_CCN_HN_F_0_ADDR 346 #endif 347 ); 348 349 350 if (dram_size < 0) { 351 ERROR("DDR init failed.\n"); 352 } 353 354 return dram_size; 355 } 356