1 /* 2 * Copyright 2018-2020 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef _SOC_H 9 #define _SOC_H 10 11 /* Chassis specific defines - common across SoC's of a particular platform */ 12 #include <dcfg_lsch3.h> 13 #include <soc_default_base_addr.h> 14 #include <soc_default_helper_macros.h> 15 16 17 #define NUM_DRAM_REGIONS 3 18 #define NXP_DRAM0_ADDR 0x80000000 19 #define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */ 20 21 #define NXP_DRAM1_ADDR 0x2080000000 22 #define NXP_DRAM1_MAX_SIZE 0x1F80000000 /* 126 G */ 23 24 #define NXP_DRAM2_ADDR 0x6000000000 25 #define NXP_DRAM2_MAX_SIZE 0x2000000000 /* 128G */ 26 27 /*DRAM0 Size defined in platform_def.h */ 28 #define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE 29 30 #define DDR_PLL_FIX 31 #define NXP_DDR_PHY1_ADDR 0x01400000 32 #define NXP_DDR_PHY2_ADDR 0x01600000 33 34 #if defined(IMAGE_BL31) 35 #define LS_SYS_TIMCTL_BASE 0x2890000 36 37 #ifdef LS_SYS_TIMCTL_BASE 38 #define PLAT_LS_NSTIMER_FRAME_ID 0 39 #define LS_CONFIG_CNTACR 1 40 #endif 41 #endif 42 43 /* Start: Macros used by soc.c: get_boot_dev */ 44 #define PORSR1_RCW_MASK 0x07800000 45 #define PORSR1_RCW_SHIFT 23 46 47 #define SDHC1_VAL 0x8 48 #define SDHC2_VAL 0x9 49 #define I2C1_VAL 0xa 50 #define FLEXSPI_NAND2K_VAL 0xc 51 #define FLEXSPI_NAND4K_VAL 0xd 52 #define FLEXSPI_NOR 0xf 53 /* End: Macros used by soc.c: get_boot_dev */ 54 55 /* bits */ 56 /* SVR Definition */ 57 #define SVR_LX2160A 0x04 58 #define SVR_LX2120A 0x14 59 #define SVR_LX2080A 0x05 60 61 /* Number of cores in platform */ 62 /* Used by common code for array initialization */ 63 #define NUMBER_OF_CLUSTERS 8 64 #define CORES_PER_CLUSTER 2 65 #define PLATFORM_CORE_COUNT NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER 66 67 /* 68 * Required LS standard platform porting definitions 69 * for CCN-508 70 */ 71 #define PLAT_CLUSTER_TO_CCN_ID_MAP 11, 15, 27, 31, 12, 28, 16, 0 72 #define PLAT_6CLUSTER_TO_CCN_ID_MAP 11, 15, 27, 31, 12, 28 73 74 75 /* Defines required for using XLAT tables from ARM common code */ 76 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40) 77 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40) 78 79 /* Clock Divisors */ 80 #define NXP_PLATFORM_CLK_DIVIDER 2 81 #define NXP_UART_CLK_DIVIDER 4 82 83 /* Start: Macros used by lx2160a.S */ 84 #define MPIDR_AFFINITY0_MASK 0x00FF 85 #define MPIDR_AFFINITY1_MASK 0xFF00 86 #define CPUECTLR_DISABLE_TWALK_PREFETCH 0x4000000000 87 #define CPUECTLR_INS_PREFETCH_MASK 0x1800000000 88 #define CPUECTLR_DAT_PREFETCH_MASK 0x0300000000 89 #define CPUECTLR_RET_8CLK 0x2 90 #define OSDLR_EL1_DLK_LOCK 0x1 91 #define CNTP_CTL_EL0_EN 0x1 92 #define CNTP_CTL_EL0_IMASK 0x2 93 /* set to 0 if the clusters are not symmetrical */ 94 #define SYMMETRICAL_CLUSTERS 1 95 /* End: Macros used by lx2160a.S */ 96 97 /* Start: Macros used by lib/psci files */ 98 #define SYSTEM_PWR_DOMAINS 1 99 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 100 NUMBER_OF_CLUSTERS + \ 101 SYSTEM_PWR_DOMAINS) 102 103 /* Power state coordination occurs at the system level */ 104 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 105 106 /* define retention state */ 107 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) 108 109 /* define power-down state */ 110 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1) 111 /* End: Macros used by lib/psci files */ 112 113 /* Some data must be aligned on the biggest cache line size in the platform. 114 * This is known only to the platform as it might have a combination of 115 * integrated and external caches. 116 * 117 * CACHE_WRITEBACK_GRANULE is defined in soc.def 118 * 119 * One cache line needed for bakery locks on ARM platforms 120 */ 121 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 122 123 #ifndef WDOG_RESET_FLAG 124 #define WDOG_RESET_FLAG DEFAULT_SET_VALUE 125 #endif 126 127 #ifndef WARM_BOOT_SUCCESS 128 #define WARM_BOOT_SUCCESS DEFAULT_SET_VALUE 129 #endif 130 131 #ifndef __ASSEMBLER__ 132 133 void set_base_freq_CNTFID0(void); 134 void soc_init_start(void); 135 void soc_init_finish(void); 136 void soc_init_percpu(void); 137 void _soc_set_start_addr(unsigned long addr); 138 void _set_platform_security(void); 139 140 #endif 141 142 #endif /* _SOC_H */ 143