187056d31SPankaj Gupta/* 287056d31SPankaj Gupta * Copyright 2018-2020 NXP 387056d31SPankaj Gupta * 487056d31SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 587056d31SPankaj Gupta * 687056d31SPankaj Gupta */ 787056d31SPankaj Gupta 887056d31SPankaj Gupta#include <arch.h> 987056d31SPankaj Gupta#include <asm_macros.S> 10*5acf82b2SAlexander Stein#include <cpu_macros.S> 1187056d31SPankaj Gupta 1287056d31SPankaj Gupta#include <platform_def.h> 1387056d31SPankaj Gupta 1487056d31SPankaj Gupta.globl plat_secondary_cold_boot_setup 1587056d31SPankaj Gupta.globl plat_is_my_cpu_primary 1687056d31SPankaj Gupta.globl plat_reset_handler 1787056d31SPankaj Gupta.globl platform_mem_init 1887056d31SPankaj Gupta 1987056d31SPankaj Gupta 2087056d31SPankaj Guptafunc platform_mem1_init 2187056d31SPankaj Gupta ret 2287056d31SPankaj Guptaendfunc platform_mem1_init 2387056d31SPankaj Gupta 2487056d31SPankaj Gupta 2587056d31SPankaj Guptafunc platform_mem_init 2687056d31SPankaj Gupta ret 2787056d31SPankaj Guptaendfunc platform_mem_init 2887056d31SPankaj Gupta 2987056d31SPankaj Gupta 3087056d31SPankaj Guptafunc apply_platform_errata 3187056d31SPankaj Gupta 3287056d31SPankaj Gupta ret 3387056d31SPankaj Guptaendfunc apply_platform_errata 3487056d31SPankaj Gupta 3587056d31SPankaj Gupta 3687056d31SPankaj Guptafunc plat_reset_handler 3787056d31SPankaj Gupta mov x29, x30 3887056d31SPankaj Gupta bl apply_platform_errata 3987056d31SPankaj Gupta 40*5acf82b2SAlexander Stein sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP 41*5acf82b2SAlexander Stein 4287056d31SPankaj Gupta#if defined(IMAGE_BL31) 4387056d31SPankaj Gupta ldr x0, =POLICY_SMMU_PAGESZ_64K 4487056d31SPankaj Gupta cbz x0, 1f 4587056d31SPankaj Gupta /* Set the SMMU page size in the sACR register */ 4687056d31SPankaj Gupta bl _set_smmu_pagesz_64 4787056d31SPankaj Gupta#endif 4887056d31SPankaj Gupta1: 4987056d31SPankaj Gupta mov x30, x29 5087056d31SPankaj Gupta 5187056d31SPankaj Gupta ret 5287056d31SPankaj Guptaendfunc plat_reset_handler 5387056d31SPankaj Gupta 5487056d31SPankaj Gupta 5587056d31SPankaj Gupta/* void plat_secondary_cold_boot_setup (void); 5687056d31SPankaj Gupta * 5787056d31SPankaj Gupta * This function performs any platform specific actions 5887056d31SPankaj Gupta * needed for a secondary cpu after a cold reset e.g 5987056d31SPankaj Gupta * mark the cpu's presence, mechanism to place it in a 6087056d31SPankaj Gupta * holding pen etc. 6187056d31SPankaj Gupta */ 6287056d31SPankaj Guptafunc plat_secondary_cold_boot_setup 6387056d31SPankaj Gupta /* lx2160a does not do cold boot for secondary CPU */ 6487056d31SPankaj Guptacb_panic: 6587056d31SPankaj Gupta b cb_panic 6687056d31SPankaj Guptaendfunc plat_secondary_cold_boot_setup 6787056d31SPankaj Gupta 6887056d31SPankaj Gupta 6987056d31SPankaj Gupta/* unsigned int plat_is_my_cpu_primary (void); 7087056d31SPankaj Gupta * 7187056d31SPankaj Gupta * Find out whether the current cpu is the primary 7287056d31SPankaj Gupta * cpu. 7387056d31SPankaj Gupta */ 7487056d31SPankaj Guptafunc plat_is_my_cpu_primary 7587056d31SPankaj Gupta mrs x0, mpidr_el1 7687056d31SPankaj Gupta and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 7787056d31SPankaj Gupta cmp x0, 0x0 7887056d31SPankaj Gupta cset w0, eq 7987056d31SPankaj Gupta ret 8087056d31SPankaj Guptaendfunc plat_is_my_cpu_primary 81