1 /* 2 * Copyright 2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <common/debug.h> 10 #include <ddr.h> 11 #include <utils.h> 12 13 #include <errata.h> 14 #include <platform_def.h> 15 16 #ifdef CONFIG_STATIC_DDR 17 #error No static value defined 18 #endif 19 20 static const struct rc_timing rce[] = { 21 {U(1600), U(8), U(8)}, 22 {U(1867), U(8), U(8)}, 23 {U(2134), U(8), U(9)}, 24 {} 25 }; 26 27 static const struct board_timing udimm[] = { 28 {U(0x04), rce, U(0x01030508), U(0x090b0d06)}, 29 {U(0x1f), rce, U(0x01030508), U(0x090b0d06)}, 30 }; 31 32 int ddr_board_options(struct ddr_info *priv) 33 { 34 int ret; 35 struct memctl_opt *popts = &priv->opt; 36 37 if (popts->rdimm != 0) { 38 debug("RDIMM parameters not set.\n"); 39 return -EINVAL; 40 } 41 42 ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm)); 43 if (ret != 0) { 44 return ret; 45 } 46 47 popts->addr_hash = 1; 48 popts->cpo_sample = U(0x7b); 49 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | 50 DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); 51 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | 52 DDR_CDR2_VREF_TRAIN_EN | 53 DDR_CDR2_VREF_RANGE_2; 54 55 return 0; 56 } 57 58 long long init_ddr(void) 59 { 60 int spd_addr[] = { NXP_SPD_EEPROM0 }; 61 struct ddr_info info; 62 struct sysinfo sys; 63 long long dram_size; 64 65 zeromem(&sys, sizeof(sys)); 66 get_clocks(&sys); 67 debug("platform clock %lu\n", sys.freq_platform); 68 debug("DDR PLL %lu\n", sys.freq_ddr_pll0); 69 70 zeromem(&info, sizeof(struct ddr_info)); 71 info.num_ctlrs = NUM_OF_DDRC; 72 info.dimm_on_ctlr = DDRC_NUM_DIMM; 73 info.clk = get_ddr_freq(&sys, 0); 74 info.spd_addr = spd_addr; 75 info.ddr[0] = (void *)NXP_DDR_ADDR; 76 77 dram_size = dram_init(&info); 78 79 if (dram_size < 0) { 80 ERROR("DDR init failed.\n"); 81 } 82 83 erratum_a008850_post(); 84 85 return dram_size; 86 } 87