1*2771dd02SJiafei Pan /* 2*2771dd02SJiafei Pan * Copyright 2022 NXP 3*2771dd02SJiafei Pan * 4*2771dd02SJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*2771dd02SJiafei Pan */ 6*2771dd02SJiafei Pan 7*2771dd02SJiafei Pan #include <errno.h> 8*2771dd02SJiafei Pan 9*2771dd02SJiafei Pan #include <common/debug.h> 10*2771dd02SJiafei Pan #include <ddr.h> 11*2771dd02SJiafei Pan #include <utils.h> 12*2771dd02SJiafei Pan 13*2771dd02SJiafei Pan #include <errata.h> 14*2771dd02SJiafei Pan #include <platform_def.h> 15*2771dd02SJiafei Pan 16*2771dd02SJiafei Pan #ifdef CONFIG_STATIC_DDR 17*2771dd02SJiafei Pan #error No static value defined 18*2771dd02SJiafei Pan #endif 19*2771dd02SJiafei Pan 20*2771dd02SJiafei Pan static const struct rc_timing rce[] = { 21*2771dd02SJiafei Pan {U(1600), U(8), U(8)}, 22*2771dd02SJiafei Pan {U(1867), U(8), U(8)}, 23*2771dd02SJiafei Pan {U(2134), U(8), U(9)}, 24*2771dd02SJiafei Pan {} 25*2771dd02SJiafei Pan }; 26*2771dd02SJiafei Pan 27*2771dd02SJiafei Pan static const struct board_timing udimm[] = { 28*2771dd02SJiafei Pan {U(0x04), rce, U(0x01030508), U(0x090b0d06)}, 29*2771dd02SJiafei Pan {U(0x1f), rce, U(0x01030508), U(0x090b0d06)}, 30*2771dd02SJiafei Pan }; 31*2771dd02SJiafei Pan 32*2771dd02SJiafei Pan int ddr_board_options(struct ddr_info *priv) 33*2771dd02SJiafei Pan { 34*2771dd02SJiafei Pan int ret; 35*2771dd02SJiafei Pan struct memctl_opt *popts = &priv->opt; 36*2771dd02SJiafei Pan 37*2771dd02SJiafei Pan if (popts->rdimm != 0) { 38*2771dd02SJiafei Pan debug("RDIMM parameters not set.\n"); 39*2771dd02SJiafei Pan return -EINVAL; 40*2771dd02SJiafei Pan } 41*2771dd02SJiafei Pan 42*2771dd02SJiafei Pan ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm)); 43*2771dd02SJiafei Pan if (ret != 0) { 44*2771dd02SJiafei Pan return ret; 45*2771dd02SJiafei Pan } 46*2771dd02SJiafei Pan 47*2771dd02SJiafei Pan popts->addr_hash = 1; 48*2771dd02SJiafei Pan popts->cpo_sample = U(0x7b); 49*2771dd02SJiafei Pan popts->ddr_cdr1 = DDR_CDR1_DHC_EN | 50*2771dd02SJiafei Pan DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); 51*2771dd02SJiafei Pan popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | 52*2771dd02SJiafei Pan DDR_CDR2_VREF_TRAIN_EN | 53*2771dd02SJiafei Pan DDR_CDR2_VREF_RANGE_2; 54*2771dd02SJiafei Pan 55*2771dd02SJiafei Pan return 0; 56*2771dd02SJiafei Pan } 57*2771dd02SJiafei Pan 58*2771dd02SJiafei Pan long long init_ddr(void) 59*2771dd02SJiafei Pan { 60*2771dd02SJiafei Pan int spd_addr[] = { NXP_SPD_EEPROM0 }; 61*2771dd02SJiafei Pan struct ddr_info info; 62*2771dd02SJiafei Pan struct sysinfo sys; 63*2771dd02SJiafei Pan long long dram_size; 64*2771dd02SJiafei Pan 65*2771dd02SJiafei Pan zeromem(&sys, sizeof(sys)); 66*2771dd02SJiafei Pan get_clocks(&sys); 67*2771dd02SJiafei Pan debug("platform clock %lu\n", sys.freq_platform); 68*2771dd02SJiafei Pan debug("DDR PLL %lu\n", sys.freq_ddr_pll0); 69*2771dd02SJiafei Pan 70*2771dd02SJiafei Pan zeromem(&info, sizeof(struct ddr_info)); 71*2771dd02SJiafei Pan info.num_ctlrs = NUM_OF_DDRC; 72*2771dd02SJiafei Pan info.dimm_on_ctlr = DDRC_NUM_DIMM; 73*2771dd02SJiafei Pan info.clk = get_ddr_freq(&sys, 0); 74*2771dd02SJiafei Pan info.spd_addr = spd_addr; 75*2771dd02SJiafei Pan info.ddr[0] = (void *)NXP_DDR_ADDR; 76*2771dd02SJiafei Pan 77*2771dd02SJiafei Pan dram_size = dram_init(&info); 78*2771dd02SJiafei Pan 79*2771dd02SJiafei Pan if (dram_size < 0) { 80*2771dd02SJiafei Pan ERROR("DDR init failed.\n"); 81*2771dd02SJiafei Pan } 82*2771dd02SJiafei Pan 83*2771dd02SJiafei Pan erratum_a008850_post(); 84*2771dd02SJiafei Pan 85*2771dd02SJiafei Pan return dram_size; 86*2771dd02SJiafei Pan } 87