1*0b0e6766SJiafei Pan /* 2*0b0e6766SJiafei Pan * Copyright 2022 NXP 3*0b0e6766SJiafei Pan * 4*0b0e6766SJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*0b0e6766SJiafei Pan */ 6*0b0e6766SJiafei Pan 7*0b0e6766SJiafei Pan #ifndef PLAT_DEF_H 8*0b0e6766SJiafei Pan #define PLAT_DEF_H 9*0b0e6766SJiafei Pan 10*0b0e6766SJiafei Pan #include <arch.h> 11*0b0e6766SJiafei Pan /* 12*0b0e6766SJiafei Pan * Required without TBBR. 13*0b0e6766SJiafei Pan * To include the defines for DDR PHY 14*0b0e6766SJiafei Pan * Images. 15*0b0e6766SJiafei Pan */ 16*0b0e6766SJiafei Pan #include <tbbr_img_def.h> 17*0b0e6766SJiafei Pan 18*0b0e6766SJiafei Pan #include <policy.h> 19*0b0e6766SJiafei Pan #include <soc.h> 20*0b0e6766SJiafei Pan 21*0b0e6766SJiafei Pan #define NXP_SPD_EEPROM0 0x51 22*0b0e6766SJiafei Pan 23*0b0e6766SJiafei Pan #define NXP_SYSCLK_FREQ 100000000 24*0b0e6766SJiafei Pan #define NXP_DDRCLK_FREQ 100000000 25*0b0e6766SJiafei Pan 26*0b0e6766SJiafei Pan /* UART related definition */ 27*0b0e6766SJiafei Pan #define NXP_CONSOLE_ADDR NXP_UART_ADDR 28*0b0e6766SJiafei Pan #define NXP_CONSOLE_BAUDRATE 115200 29*0b0e6766SJiafei Pan 30*0b0e6766SJiafei Pan /* Size of cacheable stacks */ 31*0b0e6766SJiafei Pan #if defined(IMAGE_BL2) 32*0b0e6766SJiafei Pan #if defined(TRUSTED_BOARD_BOOT) 33*0b0e6766SJiafei Pan #define PLATFORM_STACK_SIZE 0x2000 34*0b0e6766SJiafei Pan #else 35*0b0e6766SJiafei Pan #define PLATFORM_STACK_SIZE 0x1000 36*0b0e6766SJiafei Pan #endif 37*0b0e6766SJiafei Pan #elif defined(IMAGE_BL31) 38*0b0e6766SJiafei Pan #define PLATFORM_STACK_SIZE 0x1000 39*0b0e6766SJiafei Pan #endif 40*0b0e6766SJiafei Pan 41*0b0e6766SJiafei Pan #define BL2_START NXP_OCRAM_ADDR 42*0b0e6766SJiafei Pan #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 43*0b0e6766SJiafei Pan #define BL2_NOLOAD_START NXP_OCRAM_ADDR 44*0b0e6766SJiafei Pan #define BL2_NOLOAD_LIMIT BL2_BASE 45*0b0e6766SJiafei Pan 46*0b0e6766SJiafei Pan /* IO defines as needed by IO driver framework */ 47*0b0e6766SJiafei Pan #define MAX_IO_DEVICES 4 48*0b0e6766SJiafei Pan #define MAX_IO_BLOCK_DEVICES 1 49*0b0e6766SJiafei Pan #define MAX_IO_HANDLES 4 50*0b0e6766SJiafei Pan 51*0b0e6766SJiafei Pan /* 52*0b0e6766SJiafei Pan * FIP image defines - Offset at which FIP Image would be present 53*0b0e6766SJiafei Pan * Image would include Bl31 , Bl33 and Bl32 (optional) 54*0b0e6766SJiafei Pan */ 55*0b0e6766SJiafei Pan #ifdef POLICY_FUSE_PROVISION 56*0b0e6766SJiafei Pan #define MAX_FIP_DEVICES 2 57*0b0e6766SJiafei Pan #endif 58*0b0e6766SJiafei Pan 59*0b0e6766SJiafei Pan #ifndef MAX_FIP_DEVICES 60*0b0e6766SJiafei Pan #define MAX_FIP_DEVICES 1 61*0b0e6766SJiafei Pan #endif 62*0b0e6766SJiafei Pan 63*0b0e6766SJiafei Pan #define BL32_IRQ_SEC_PHY_TIMER 29 64*0b0e6766SJiafei Pan #define BL31_WDOG_SEC 89 65*0b0e6766SJiafei Pan 66*0b0e6766SJiafei Pan /* 67*0b0e6766SJiafei Pan * ID of the secure physical generic timer interrupt used by the BL32. 68*0b0e6766SJiafei Pan */ 69*0b0e6766SJiafei Pan #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 70*0b0e6766SJiafei Pan INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 71*0b0e6766SJiafei Pan GIC_INTR_CFG_LEVEL) 72*0b0e6766SJiafei Pan 73*0b0e6766SJiafei Pan /* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ 74*0b0e6766SJiafei Pan #define PLAT_LS_G0_IRQ_PROPS(grp) \ 75*0b0e6766SJiafei Pan INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 76*0b0e6766SJiafei Pan GIC_INTR_CFG_EDGE), \ 77*0b0e6766SJiafei Pan INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \ 78*0b0e6766SJiafei Pan GIC_INTR_CFG_LEVEL) 79*0b0e6766SJiafei Pan 80*0b0e6766SJiafei Pan 81*0b0e6766SJiafei Pan #endif /* PLAT_DEF_H */ 82