1*9df5ba05SJiafei Pan/* 2*9df5ba05SJiafei Pan * Copyright 2022 NXP 3*9df5ba05SJiafei Pan * 4*9df5ba05SJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*9df5ba05SJiafei Pan */ 6*9df5ba05SJiafei Pan 7*9df5ba05SJiafei Pan#include <arch.h> 8*9df5ba05SJiafei Pan#include <asm_macros.S> 9*9df5ba05SJiafei Pan#include <platform_def.h> 10*9df5ba05SJiafei Pan 11*9df5ba05SJiafei Pan .globl plat_secondary_cold_boot_setup 12*9df5ba05SJiafei Pan .globl plat_is_my_cpu_primary 13*9df5ba05SJiafei Pan .globl plat_reset_handler 14*9df5ba05SJiafei Pan .globl platform_mem_init 15*9df5ba05SJiafei Pan 16*9df5ba05SJiafei Panfunc platform_mem1_init 17*9df5ba05SJiafei Pan ret 18*9df5ba05SJiafei Panendfunc platform_mem1_init 19*9df5ba05SJiafei Pan 20*9df5ba05SJiafei Panfunc platform_mem_init 21*9df5ba05SJiafei Pan ret 22*9df5ba05SJiafei Panendfunc platform_mem_init 23*9df5ba05SJiafei Pan 24*9df5ba05SJiafei Panfunc apply_platform_errata 25*9df5ba05SJiafei Pan ret 26*9df5ba05SJiafei Panendfunc apply_platform_errata 27*9df5ba05SJiafei Pan 28*9df5ba05SJiafei Panfunc plat_reset_handler 29*9df5ba05SJiafei Pan mov x29, x30 30*9df5ba05SJiafei Pan bl apply_platform_errata 31*9df5ba05SJiafei Pan 32*9df5ba05SJiafei Pan#if defined(IMAGE_BL31) 33*9df5ba05SJiafei Pan ldr x0, =POLICY_SMMU_PAGESZ_64K 34*9df5ba05SJiafei Pan cbz x0, 1f 35*9df5ba05SJiafei Pan /* Set the SMMU page size in the sACR register */ 36*9df5ba05SJiafei Pan bl _set_smmu_pagesz_64 37*9df5ba05SJiafei Pan#endif 38*9df5ba05SJiafei Pan1: 39*9df5ba05SJiafei Pan mov x30, x29 40*9df5ba05SJiafei Pan ret 41*9df5ba05SJiafei Panendfunc plat_reset_handler 42*9df5ba05SJiafei Pan 43*9df5ba05SJiafei Pan /* 44*9df5ba05SJiafei Pan * void plat_secondary_cold_boot_setup (void); 45*9df5ba05SJiafei Pan * 46*9df5ba05SJiafei Pan * This function performs any platform specific actions 47*9df5ba05SJiafei Pan * needed for a secondary cpu after a cold reset e.g 48*9df5ba05SJiafei Pan * mark the cpu's presence, mechanism to place it in a 49*9df5ba05SJiafei Pan * holding pen etc. 50*9df5ba05SJiafei Pan */ 51*9df5ba05SJiafei Panfunc plat_secondary_cold_boot_setup 52*9df5ba05SJiafei Pan /* ls1088a does not do cold boot for secondary CPU */ 53*9df5ba05SJiafei Pancb_panic: 54*9df5ba05SJiafei Pan b cb_panic 55*9df5ba05SJiafei Panendfunc plat_secondary_cold_boot_setup 56*9df5ba05SJiafei Pan 57*9df5ba05SJiafei Pan /* 58*9df5ba05SJiafei Pan * unsigned int plat_is_my_cpu_primary (void); 59*9df5ba05SJiafei Pan * 60*9df5ba05SJiafei Pan * Find out whether the current cpu is the primary 61*9df5ba05SJiafei Pan * cpu. 62*9df5ba05SJiafei Pan */ 63*9df5ba05SJiafei Panfunc plat_is_my_cpu_primary 64*9df5ba05SJiafei Pan mrs x0, mpidr_el1 65*9df5ba05SJiafei Pan and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 66*9df5ba05SJiafei Pan cmp x0, 0x0 67*9df5ba05SJiafei Pan cset w0, eq 68*9df5ba05SJiafei Pan ret 69*9df5ba05SJiafei Panendfunc plat_is_my_cpu_primary 70