1 /*
2 * Copyright 2018-2022, 2025 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch.h>
10 #include <caam.h>
11 #include <cassert.h>
12 #include <cci.h>
13 #include <common/debug.h>
14 #include <dcfg.h>
15 #ifdef I2C_INIT
16 #include <i2c.h>
17 #endif
18 #include <lib/mmio.h>
19 #include <lib/xlat_tables/xlat_tables_v2.h>
20 #include <ls_interconnect.h>
21 #ifdef POLICY_FUSE_PROVISION
22 #include <nxp_gpio.h>
23 #endif
24 #include <nxp_smmu.h>
25 #include <nxp_timer.h>
26 #include <plat_console.h>
27 #include <plat_gic.h>
28 #include <plat_tzc400.h>
29 #include <scfg.h>
30 #if defined(NXP_SFP_ENABLED)
31 #include <sfp.h>
32 #endif
33 #if TRUSTED_BOARD_BOOT
34 #include <snvs.h>
35 #endif
36
37 #include <errata.h>
38 #include <ns_access.h>
39 #ifdef CONFIG_OCRAM_ECC_EN
40 #include <ocram.h>
41 #endif
42 #include <plat_common.h>
43 #include <platform_def.h>
44 #include <soc.h>
45
46 static dcfg_init_info_t dcfg_init_data = {
47 .g_nxp_dcfg_addr = NXP_DCFG_ADDR,
48 .nxp_sysclk_freq = NXP_SYSCLK_FREQ,
49 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
50 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
51 };
52
53 /* Function to return the SoC SYS CLK */
get_sys_clk(void)54 static unsigned int get_sys_clk(void)
55 {
56 return NXP_SYSCLK_FREQ;
57 }
58
59 /*
60 * Function returns the base counter frequency
61 * after reading the first entry at CNTFID0 (0x20 offset).
62 *
63 * Function is used by:
64 * 1. ARM common code for PSCI management.
65 * 2. ARM Generic Timer init.
66 *
67 */
plat_get_syscnt_freq2(void)68 unsigned int plat_get_syscnt_freq2(void)
69 {
70 unsigned int counter_base_frequency;
71
72 counter_base_frequency = get_sys_clk() / 4;
73
74 return counter_base_frequency;
75 }
76
77 #ifdef IMAGE_BL2
78 /* Functions for BL2 */
79
80 static struct soc_type soc_list[] = {
81 SOC_ENTRY(LS1046A, LS1046A, 1, 4),
82 SOC_ENTRY(LS1046AE, LS1046AE, 1, 4),
83 SOC_ENTRY(LS1026A, LS1026A, 1, 2),
84 SOC_ENTRY(LS1026AE, LS1026AE, 1, 2),
85 };
86
87 #ifdef POLICY_FUSE_PROVISION
88 static gpio_init_info_t gpio_init_data = {
89 .gpio1_base_addr = NXP_GPIO1_ADDR,
90 .gpio2_base_addr = NXP_GPIO2_ADDR,
91 .gpio3_base_addr = NXP_GPIO3_ADDR,
92 .gpio4_base_addr = NXP_GPIO4_ADDR,
93 };
94 #endif
95
96 /*
97 * Function to set the base counter frequency at
98 * the first entry of the Frequency Mode Table,
99 * at CNTFID0 (0x20 offset).
100 *
101 * Set the value of the pirmary core register cntfrq_el0.
102 */
set_base_freq_CNTFID0(void)103 static void set_base_freq_CNTFID0(void)
104 {
105 /*
106 * Below register specifies the base frequency of the system counter.
107 * As per NXP Board Manuals:
108 * The system counter always works with SYS_REF_CLK/4 frequency clock.
109 */
110 unsigned int counter_base_frequency = get_sys_clk() / 4;
111
112 /* Setting the frequency in the Frequency modes table.
113 *
114 * Note: The value for ls1046ardb board at this offset
115 * is not RW as stated. This offset have the
116 * fixed value of 100000400 Hz.
117 *
118 * The below code line has no effect.
119 * Keeping it for other platforms where it has effect.
120 */
121 mmio_write_32(NXP_TIMER_ADDR + CNTFID_OFF, counter_base_frequency);
122
123 write_cntfrq_el0(counter_base_frequency);
124 }
125
soc_preload_setup(void)126 void soc_preload_setup(void)
127 {
128
129 }
130
131 /*
132 * This function implements soc specific erratas
133 * This is called before DDR is initialized or MMU is enabled
134 */
soc_early_init(void)135 void soc_early_init(void)
136 {
137 uint8_t num_clusters, cores_per_cluster;
138 dram_regions_info_t *dram_regions_info = get_dram_regions_info();
139
140 #if TRUSTED_BOARD_BOOT
141 snvs_init(NXP_SNVS_ADDR);
142 #endif
143
144 #ifdef CONFIG_OCRAM_ECC_EN
145 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE);
146 #endif
147 dcfg_init(&dcfg_init_data);
148 #ifdef POLICY_FUSE_PROVISION
149 gpio_init(&gpio_init_data);
150 sec_init(NXP_CAAM_ADDR);
151 #endif
152 #if LOG_LEVEL > 0
153 /* Initialize the console to provide early debug support */
154
155 plat_console_init(NXP_CONSOLE_ADDR,
156 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
157 #endif
158 set_base_freq_CNTFID0();
159
160 /* Enable snooping on SEC read and write transactions */
161 scfg_setbits32((void *)(NXP_SCFG_ADDR + SCFG_SNPCNFGCR_OFFSET),
162 SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP);
163
164 /*
165 * Initialize Interconnect for this cluster during cold boot.
166 * No need for locks as no other CPU is active.
167 */
168 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
169
170 /*
171 * Enable Interconnect coherency for the primary CPU's cluster.
172 */
173 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
174 plat_ls_interconnect_enter_coherency(num_clusters);
175
176 /*
177 * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
178 */
179 smmu_cache_unlock(NXP_SMMU_ADDR);
180 INFO("SMMU Cache Unlocking is Configured.\n");
181
182 #if TRUSTED_BOARD_BOOT
183 uint32_t mode;
184
185 sfp_init(NXP_SFP_ADDR);
186 /*
187 * For secure boot disable SMMU.
188 * Later when platform security policy comes in picture,
189 * this might get modified based on the policy
190 */
191 if (check_boot_mode_secure(&mode) == true) {
192 bypass_smmu(NXP_SMMU_ADDR);
193 }
194
195 /*
196 * For Mbedtls currently crypto is not supported via CAAM
197 * enable it when that support is there. In tbbr.mk
198 * the CAAM_INTEG is set as 0.
199 */
200 #ifndef MBEDTLS_X509
201 /* Initialize the crypto accelerator if enabled */
202 if (is_sec_enabled() == false) {
203 INFO("SEC is disabled.\n");
204 } else {
205 sec_init(NXP_CAAM_ADDR);
206 }
207 #endif
208 #elif defined(POLICY_FUSE_PROVISION)
209 gpio_init(&gpio_init_data);
210 sfp_init(NXP_SFP_ADDR);
211 sec_init(NXP_CAAM_ADDR);
212 #endif
213
214 soc_errata();
215
216 /* Initialize system level generic timer for Layerscape Socs. */
217 delay_timer_init(NXP_TIMER_ADDR);
218
219 #ifdef DDR_INIT
220 i2c_init(NXP_I2C_ADDR);
221 dram_regions_info->total_dram_size = init_ddr();
222 #endif
223 }
224
soc_bl2_prepare_exit(void)225 void soc_bl2_prepare_exit(void)
226 {
227 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
228 set_sfp_wr_disable();
229 #endif
230 }
231
232 /* This function returns the boot device based on RCW_SRC */
get_boot_dev(void)233 enum boot_device get_boot_dev(void)
234 {
235 enum boot_device src = BOOT_DEVICE_NONE;
236 uint32_t porsr1;
237 uint32_t rcw_src, val;
238
239 porsr1 = read_reg_porsr1();
240
241 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
242
243 val = rcw_src & RCW_SRC_NAND_MASK;
244
245 if (val == RCW_SRC_NAND_VAL) {
246 val = rcw_src & NAND_RESERVED_MASK;
247 if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) {
248 src = BOOT_DEVICE_IFC_NAND;
249 INFO("RCW BOOT SRC is IFC NAND\n");
250 }
251 } else {
252 /* RCW SRC NOR */
253 val = rcw_src & RCW_SRC_NOR_MASK;
254 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
255 src = BOOT_DEVICE_IFC_NOR;
256 INFO("RCW BOOT SRC is IFC NOR\n");
257 } else {
258 switch (rcw_src) {
259 case QSPI_VAL1:
260 case QSPI_VAL2:
261 src = BOOT_DEVICE_QSPI;
262 INFO("RCW BOOT SRC is QSPI\n");
263 break;
264 case SD_VAL:
265 src = BOOT_DEVICE_EMMC;
266 INFO("RCW BOOT SRC is SD/EMMC\n");
267 break;
268 default:
269 src = BOOT_DEVICE_NONE;
270 }
271 }
272 }
273
274 return src;
275 }
276
277 /* This function sets up access permissions on memory regions */
soc_mem_access(void)278 void soc_mem_access(void)
279 {
280 dram_regions_info_t *info_dram_regions = get_dram_regions_info();
281 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION];
282 unsigned int dram_idx, index = 0U;
283
284 for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions;
285 dram_idx++) {
286 if (info_dram_regions->region[dram_idx].size == 0) {
287 ERROR("DDR init failure, or");
288 ERROR("DRAM regions not populated correctly.\n");
289 break;
290 }
291
292 index = populate_tzc400_reg_list(tzc400_reg_list,
293 dram_idx, index,
294 info_dram_regions->region[dram_idx].addr,
295 info_dram_regions->region[dram_idx].size,
296 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
297 }
298
299 mem_access_setup(NXP_TZC_ADDR, index, tzc400_reg_list);
300 }
301
302 #else /* IMAGE_BL2 */
303 /* Functions for BL31 */
304
305 const unsigned char _power_domain_tree_desc[] = {1, 1, 4};
306
307 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
308 assert_invalid_ls1046_cluster_count);
309
310 /* This function returns the SoC topology */
plat_get_power_domain_tree_desc(void)311 const unsigned char *plat_get_power_domain_tree_desc(void)
312 {
313 return _power_domain_tree_desc;
314 }
315
316 /*
317 * This function returns the core count within the cluster corresponding to
318 * `mpidr`.
319 */
plat_ls_get_cluster_core_count(u_register_t mpidr)320 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
321 {
322 return CORES_PER_CLUSTER;
323 }
324
soc_early_platform_setup2(void)325 void soc_early_platform_setup2(void)
326 {
327 dcfg_init(&dcfg_init_data);
328 /* Initialize system level generic timer for SoCs */
329 delay_timer_init(NXP_TIMER_ADDR);
330
331 #if LOG_LEVEL > 0
332 /* Initialize the console to provide early debug support */
333 plat_console_init(NXP_CONSOLE_ADDR,
334 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
335 #endif
336 }
337
soc_platform_setup(void)338 void soc_platform_setup(void)
339 {
340 static uint32_t target_mask_array[PLATFORM_CORE_COUNT];
341 /*
342 * On a GICv2 system, the Group 1 secure interrupts are treated
343 * as Group 0 interrupts.
344 */
345 static interrupt_prop_t ls_interrupt_props[] = {
346 PLAT_LS_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
347 PLAT_LS_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
348 };
349
350 plat_ls_gic_driver_init(
351 #if (TEST_BL31)
352 /* Defect in simulator - GIC base addresses (4Kb aligned) */
353 NXP_GICD_4K_ADDR,
354 NXP_GICC_4K_ADDR,
355 #else
356 NXP_GICD_64K_ADDR,
357 NXP_GICC_64K_ADDR,
358 #endif
359 PLATFORM_CORE_COUNT,
360 ls_interrupt_props,
361 ARRAY_SIZE(ls_interrupt_props),
362 target_mask_array);
363
364 plat_ls_gic_init();
365 enable_init_timer();
366 }
367
368 /* This function initializes the soc from the BL31 module */
soc_init(void)369 void soc_init(void)
370 {
371 /* low-level init of the soc */
372 soc_init_lowlevel();
373 _init_global_data();
374 soc_init_percpu();
375 _initialize_psci();
376
377 /*
378 * Initialize the interconnect during cold boot.
379 * No need for locks as no other CPU is active.
380 */
381 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map));
382
383 /*
384 * Enable coherency in interconnect for the primary CPU's cluster.
385 * Earlier bootloader stages might already do this but we can't
386 * assume so. No harm in executing this code twice.
387 */
388 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
389
390 /* Init CSU to enable non-secure access to peripherals */
391 enable_layerscape_ns_access(ns_dev, ARRAY_SIZE(ns_dev), NXP_CSU_ADDR);
392
393 /* Initialize the crypto accelerator if enabled */
394 if (is_sec_enabled() == false) {
395 INFO("SEC is disabled.\n");
396 } else {
397 sec_init(NXP_CAAM_ADDR);
398 }
399 }
400
soc_runtime_setup(void)401 void soc_runtime_setup(void)
402 {
403
404 }
405
406 #endif /* IMAGE_BL2 */
407