1*bb52f756SJiafei Pan /* 2*bb52f756SJiafei Pan * Copyright 2018-2022 NXP 3*bb52f756SJiafei Pan * 4*bb52f756SJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*bb52f756SJiafei Pan */ 6*bb52f756SJiafei Pan 7*bb52f756SJiafei Pan #ifndef PLAT_DEF_H 8*bb52f756SJiafei Pan #define PLAT_DEF_H 9*bb52f756SJiafei Pan 10*bb52f756SJiafei Pan #include <arch.h> 11*bb52f756SJiafei Pan /* 12*bb52f756SJiafei Pan * Required without TBBR. 13*bb52f756SJiafei Pan * To include the defines for DDR PHY Images. 14*bb52f756SJiafei Pan */ 15*bb52f756SJiafei Pan #include <tbbr_img_def.h> 16*bb52f756SJiafei Pan 17*bb52f756SJiafei Pan #include "policy.h" 18*bb52f756SJiafei Pan #include <soc.h> 19*bb52f756SJiafei Pan 20*bb52f756SJiafei Pan #define NXP_SPD_EEPROM0 0x51 21*bb52f756SJiafei Pan 22*bb52f756SJiafei Pan #define NXP_SYSCLK_FREQ 100000000 23*bb52f756SJiafei Pan #define NXP_DDRCLK_FREQ 100000000 24*bb52f756SJiafei Pan 25*bb52f756SJiafei Pan /* UART related definition */ 26*bb52f756SJiafei Pan #define NXP_CONSOLE_ADDR NXP_UART_ADDR 27*bb52f756SJiafei Pan #define NXP_CONSOLE_BAUDRATE 115200 28*bb52f756SJiafei Pan 29*bb52f756SJiafei Pan /* Size of cacheable stacks */ 30*bb52f756SJiafei Pan #if defined(IMAGE_BL2) 31*bb52f756SJiafei Pan #if defined(TRUSTED_BOARD_BOOT) 32*bb52f756SJiafei Pan #define PLATFORM_STACK_SIZE 0x2000 33*bb52f756SJiafei Pan #else 34*bb52f756SJiafei Pan #define PLATFORM_STACK_SIZE 0x1000 35*bb52f756SJiafei Pan #endif 36*bb52f756SJiafei Pan #elif defined(IMAGE_BL31) 37*bb52f756SJiafei Pan #define PLATFORM_STACK_SIZE 0x1000 38*bb52f756SJiafei Pan #endif 39*bb52f756SJiafei Pan 40*bb52f756SJiafei Pan /* SD block buffer */ 41*bb52f756SJiafei Pan #define NXP_SD_BLOCK_BUF_SIZE (0x00100000) 42*bb52f756SJiafei Pan #define NXP_SD_BLOCK_BUF_ADDR ULL(0x80000000) 43*bb52f756SJiafei Pan 44*bb52f756SJiafei Pan #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 45*bb52f756SJiafei Pan 46*bb52f756SJiafei Pan /* IO defines as needed by IO driver framework */ 47*bb52f756SJiafei Pan #define MAX_IO_DEVICES U(3) 48*bb52f756SJiafei Pan #define MAX_IO_BLOCK_DEVICES U(1) 49*bb52f756SJiafei Pan #define MAX_IO_HANDLES U(4) 50*bb52f756SJiafei Pan 51*bb52f756SJiafei Pan /* 52*bb52f756SJiafei Pan * FIP image defines - Offset at which FIP Image would be present 53*bb52f756SJiafei Pan * Image would include Bl31 , Bl33 and Bl32 (optional) 54*bb52f756SJiafei Pan */ 55*bb52f756SJiafei Pan #ifdef POLICY_FUSE_PROVISION 56*bb52f756SJiafei Pan #define MAX_FIP_DEVICES U(2) 57*bb52f756SJiafei Pan #endif 58*bb52f756SJiafei Pan 59*bb52f756SJiafei Pan #ifndef MAX_FIP_DEVICES 60*bb52f756SJiafei Pan #define MAX_FIP_DEVICES U(1) 61*bb52f756SJiafei Pan #endif 62*bb52f756SJiafei Pan 63*bb52f756SJiafei Pan /* 64*bb52f756SJiafei Pan * ID of the secure physical generic timer interrupt used by the BL32. 65*bb52f756SJiafei Pan */ 66*bb52f756SJiafei Pan #define BL32_IRQ_SEC_PHY_TIMER 29 67*bb52f756SJiafei Pan 68*bb52f756SJiafei Pan /* 69*bb52f756SJiafei Pan * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 70*bb52f756SJiafei Pan * terminology. On a GICv2 system or mode, the lists will be merged and treated 71*bb52f756SJiafei Pan * as Group 0 interrupts. 72*bb52f756SJiafei Pan */ 73*bb52f756SJiafei Pan #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 74*bb52f756SJiafei Pan INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 75*bb52f756SJiafei Pan GIC_INTR_CFG_LEVEL) 76*bb52f756SJiafei Pan 77*bb52f756SJiafei Pan #define PLAT_LS_G0_IRQ_PROPS(grp) 78*bb52f756SJiafei Pan 79*bb52f756SJiafei Pan #endif /* PLAT_DEF_H */ 80