1*16662dc4SJiafei Pan /* 2*16662dc4SJiafei Pan * Copyright 2018-2022 NXP 3*16662dc4SJiafei Pan * 4*16662dc4SJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*16662dc4SJiafei Pan */ 6*16662dc4SJiafei Pan 7*16662dc4SJiafei Pan #ifndef PLAT_DEF_H 8*16662dc4SJiafei Pan #define PLAT_DEF_H 9*16662dc4SJiafei Pan 10*16662dc4SJiafei Pan #include <arch.h> 11*16662dc4SJiafei Pan /* Required without TBBR. 12*16662dc4SJiafei Pan * To include the defines for DDR PHY 13*16662dc4SJiafei Pan * Images. 14*16662dc4SJiafei Pan */ 15*16662dc4SJiafei Pan #include <tbbr_img_def.h> 16*16662dc4SJiafei Pan 17*16662dc4SJiafei Pan #include <policy.h> 18*16662dc4SJiafei Pan #include <soc.h> 19*16662dc4SJiafei Pan 20*16662dc4SJiafei Pan #define NXP_SPD_EEPROM0 0x51 21*16662dc4SJiafei Pan 22*16662dc4SJiafei Pan #define NXP_SYSCLK_FREQ 100000000 23*16662dc4SJiafei Pan #define NXP_DDRCLK_FREQ 100000000 24*16662dc4SJiafei Pan 25*16662dc4SJiafei Pan /* UART related definition */ 26*16662dc4SJiafei Pan #define NXP_CONSOLE_ADDR NXP_UART_ADDR 27*16662dc4SJiafei Pan #define NXP_CONSOLE_BAUDRATE 115200 28*16662dc4SJiafei Pan 29*16662dc4SJiafei Pan /* Size of cacheable stacks */ 30*16662dc4SJiafei Pan #if defined(IMAGE_BL2) 31*16662dc4SJiafei Pan #if defined(TRUSTED_BOARD_BOOT) 32*16662dc4SJiafei Pan #define PLATFORM_STACK_SIZE 0x2000 33*16662dc4SJiafei Pan #else 34*16662dc4SJiafei Pan #define PLATFORM_STACK_SIZE 0x1000 35*16662dc4SJiafei Pan #endif 36*16662dc4SJiafei Pan #elif defined(IMAGE_BL31) 37*16662dc4SJiafei Pan #define PLATFORM_STACK_SIZE 0x1000 38*16662dc4SJiafei Pan #endif 39*16662dc4SJiafei Pan 40*16662dc4SJiafei Pan /* SD block buffer */ 41*16662dc4SJiafei Pan #define NXP_SD_BLOCK_BUF_SIZE (0x00100000) 42*16662dc4SJiafei Pan #define NXP_SD_BLOCK_BUF_ADDR ULL(0x80000000) 43*16662dc4SJiafei Pan 44*16662dc4SJiafei Pan #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 45*16662dc4SJiafei Pan 46*16662dc4SJiafei Pan /* IO defines as needed by IO driver framework */ 47*16662dc4SJiafei Pan #define MAX_IO_DEVICES U(3) 48*16662dc4SJiafei Pan #define MAX_IO_BLOCK_DEVICES U(1) 49*16662dc4SJiafei Pan #define MAX_IO_HANDLES U(4) 50*16662dc4SJiafei Pan 51*16662dc4SJiafei Pan /* 52*16662dc4SJiafei Pan * FIP image defines - Offset at which FIP Image would be present 53*16662dc4SJiafei Pan * Image would include Bl31 , Bl33 and Bl32 (optional) 54*16662dc4SJiafei Pan */ 55*16662dc4SJiafei Pan #ifdef POLICY_FUSE_PROVISION 56*16662dc4SJiafei Pan #define MAX_FIP_DEVICES U(2) 57*16662dc4SJiafei Pan #endif 58*16662dc4SJiafei Pan 59*16662dc4SJiafei Pan #ifndef MAX_FIP_DEVICES 60*16662dc4SJiafei Pan #define MAX_FIP_DEVICES U(1) 61*16662dc4SJiafei Pan #endif 62*16662dc4SJiafei Pan 63*16662dc4SJiafei Pan /* 64*16662dc4SJiafei Pan * ID of the secure physical generic timer interrupt used by the BL32. 65*16662dc4SJiafei Pan */ 66*16662dc4SJiafei Pan #define BL32_IRQ_SEC_PHY_TIMER 29 67*16662dc4SJiafei Pan 68*16662dc4SJiafei Pan /* 69*16662dc4SJiafei Pan * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 70*16662dc4SJiafei Pan * terminology. On a GICv2 system or mode, the lists will be merged and treated 71*16662dc4SJiafei Pan * as Group 0 interrupts. 72*16662dc4SJiafei Pan */ 73*16662dc4SJiafei Pan #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 74*16662dc4SJiafei Pan INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 75*16662dc4SJiafei Pan GIC_INTR_CFG_LEVEL) 76*16662dc4SJiafei Pan 77*16662dc4SJiafei Pan #define PLAT_LS_G0_IRQ_PROPS(grp) 78*16662dc4SJiafei Pan 79*16662dc4SJiafei Pan #endif 80