1*cc708597SJiafei Pan/* 2*cc708597SJiafei Pan * Copyright 2018-2022 NXP 3*cc708597SJiafei Pan * 4*cc708597SJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*cc708597SJiafei Pan * 6*cc708597SJiafei Pan */ 7*cc708597SJiafei Pan 8*cc708597SJiafei Pan#include <arch.h> 9*cc708597SJiafei Pan#include <asm_macros.S> 10*cc708597SJiafei Pan 11*cc708597SJiafei Pan#include <platform_def.h> 12*cc708597SJiafei Pan 13*cc708597SJiafei Pan .globl plat_secondary_cold_boot_setup 14*cc708597SJiafei Pan .globl plat_is_my_cpu_primary 15*cc708597SJiafei Pan .globl plat_reset_handler 16*cc708597SJiafei Pan .globl platform_mem_init 17*cc708597SJiafei Pan 18*cc708597SJiafei Panfunc platform_mem1_init 19*cc708597SJiafei Pan ret 20*cc708597SJiafei Panendfunc platform_mem1_init 21*cc708597SJiafei Pan 22*cc708597SJiafei Panfunc platform_mem_init 23*cc708597SJiafei Pan ret 24*cc708597SJiafei Panendfunc platform_mem_init 25*cc708597SJiafei Pan 26*cc708597SJiafei Panfunc l2_mem_init 27*cc708597SJiafei Pan /* Initialize the L2 RAM latency */ 28*cc708597SJiafei Pan mrs x1, S3_1_c11_c0_2 29*cc708597SJiafei Pan mov x0, #0x1C7 30*cc708597SJiafei Pan /* Clear L2 Tag RAM latency and L2 Data RAM latency */ 31*cc708597SJiafei Pan bic x1, x1, x0 32*cc708597SJiafei Pan /* Set L2 data ram latency bits [2:0] */ 33*cc708597SJiafei Pan orr x1, x1, #0x2 34*cc708597SJiafei Pan /* set L2 tag ram latency bits [8:6] */ 35*cc708597SJiafei Pan orr x1, x1, #0x80 36*cc708597SJiafei Pan msr S3_1_c11_c0_2, x1 37*cc708597SJiafei Pan isb 38*cc708597SJiafei Pan ret 39*cc708597SJiafei Panendfunc l2_mem_init 40*cc708597SJiafei Pan 41*cc708597SJiafei Panfunc apply_platform_errata 42*cc708597SJiafei Pan ret 43*cc708597SJiafei Panendfunc apply_platform_errata 44*cc708597SJiafei Pan 45*cc708597SJiafei Panfunc plat_reset_handler 46*cc708597SJiafei Pan mov x29, x30 47*cc708597SJiafei Pan#if (defined(IMAGE_BL2) && BL2_AT_EL3) 48*cc708597SJiafei Pan bl l2_mem_init 49*cc708597SJiafei Pan#endif 50*cc708597SJiafei Pan bl apply_platform_errata 51*cc708597SJiafei Pan 52*cc708597SJiafei Pan#if defined(IMAGE_BL31) 53*cc708597SJiafei Pan ldr x0, =POLICY_SMMU_PAGESZ_64K 54*cc708597SJiafei Pan cbz x0, 1f 55*cc708597SJiafei Pan /* Set the SMMU page size in the SACR register */ 56*cc708597SJiafei Pan bl _set_smmu_pagesz_64 57*cc708597SJiafei Pan#endif 58*cc708597SJiafei Pan1: 59*cc708597SJiafei Pan /* 60*cc708597SJiafei Pan * May be cntfrq_el0 needs to be assigned 61*cc708597SJiafei Pan * the value COUNTER_FREQUENCY 62*cc708597SJiafei Pan */ 63*cc708597SJiafei Pan mov x30, x29 64*cc708597SJiafei Pan ret 65*cc708597SJiafei Panendfunc plat_reset_handler 66*cc708597SJiafei Pan 67*cc708597SJiafei Pan/* 68*cc708597SJiafei Pan * void plat_secondary_cold_boot_setup (void); 69*cc708597SJiafei Pan * 70*cc708597SJiafei Pan * This function performs any platform specific actions 71*cc708597SJiafei Pan * needed for a secondary cpu after a cold reset e.g 72*cc708597SJiafei Pan * mark the cpu's presence, mechanism to place it in a 73*cc708597SJiafei Pan * holding pen etc. 74*cc708597SJiafei Pan */ 75*cc708597SJiafei Panfunc plat_secondary_cold_boot_setup 76*cc708597SJiafei Pan /* ls1046a does not do cold boot for secondary CPU */ 77*cc708597SJiafei Pancb_panic: 78*cc708597SJiafei Pan b cb_panic 79*cc708597SJiafei Panendfunc plat_secondary_cold_boot_setup 80*cc708597SJiafei Pan 81*cc708597SJiafei Pan/* 82*cc708597SJiafei Pan * unsigned int plat_is_my_cpu_primary (void); 83*cc708597SJiafei Pan * 84*cc708597SJiafei Pan * Find out whether the current cpu is the primary cpu. 85*cc708597SJiafei Pan */ 86*cc708597SJiafei Panfunc plat_is_my_cpu_primary 87*cc708597SJiafei Pan mrs x0, mpidr_el1 88*cc708597SJiafei Pan and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 89*cc708597SJiafei Pan cmp x0, 0x0 90*cc708597SJiafei Pan cset w0, eq 91*cc708597SJiafei Pan ret 92*cc708597SJiafei Panendfunc plat_is_my_cpu_primary 93