1cc708597SJiafei Pan/* 2cc708597SJiafei Pan * Copyright 2018-2022 NXP 3cc708597SJiafei Pan * 4cc708597SJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5cc708597SJiafei Pan * 6cc708597SJiafei Pan */ 7cc708597SJiafei Pan 8cc708597SJiafei Pan#include <arch.h> 9cc708597SJiafei Pan#include <asm_macros.S> 10cc708597SJiafei Pan 11cc708597SJiafei Pan#include <platform_def.h> 12cc708597SJiafei Pan 13cc708597SJiafei Pan .globl plat_secondary_cold_boot_setup 14cc708597SJiafei Pan .globl plat_is_my_cpu_primary 15cc708597SJiafei Pan .globl plat_reset_handler 16cc708597SJiafei Pan .globl platform_mem_init 17cc708597SJiafei Pan 18cc708597SJiafei Panfunc platform_mem1_init 19cc708597SJiafei Pan ret 20cc708597SJiafei Panendfunc platform_mem1_init 21cc708597SJiafei Pan 22cc708597SJiafei Panfunc platform_mem_init 23cc708597SJiafei Pan ret 24cc708597SJiafei Panendfunc platform_mem_init 25cc708597SJiafei Pan 26cc708597SJiafei Panfunc l2_mem_init 27cc708597SJiafei Pan /* Initialize the L2 RAM latency */ 28cc708597SJiafei Pan mrs x1, S3_1_c11_c0_2 29cc708597SJiafei Pan mov x0, #0x1C7 30cc708597SJiafei Pan /* Clear L2 Tag RAM latency and L2 Data RAM latency */ 31cc708597SJiafei Pan bic x1, x1, x0 32cc708597SJiafei Pan /* Set L2 data ram latency bits [2:0] */ 33cc708597SJiafei Pan orr x1, x1, #0x2 34cc708597SJiafei Pan /* set L2 tag ram latency bits [8:6] */ 35cc708597SJiafei Pan orr x1, x1, #0x80 36cc708597SJiafei Pan msr S3_1_c11_c0_2, x1 37cc708597SJiafei Pan isb 38cc708597SJiafei Pan ret 39cc708597SJiafei Panendfunc l2_mem_init 40cc708597SJiafei Pan 41cc708597SJiafei Panfunc apply_platform_errata 42cc708597SJiafei Pan ret 43cc708597SJiafei Panendfunc apply_platform_errata 44cc708597SJiafei Pan 45cc708597SJiafei Panfunc plat_reset_handler 46cc708597SJiafei Pan mov x29, x30 47*42d4d3baSArvind Ram Prakash#if (defined(IMAGE_BL2) && RESET_TO_BL2) 48cc708597SJiafei Pan bl l2_mem_init 49cc708597SJiafei Pan#endif 50cc708597SJiafei Pan bl apply_platform_errata 51cc708597SJiafei Pan 52cc708597SJiafei Pan#if defined(IMAGE_BL31) 53cc708597SJiafei Pan ldr x0, =POLICY_SMMU_PAGESZ_64K 54cc708597SJiafei Pan cbz x0, 1f 55cc708597SJiafei Pan /* Set the SMMU page size in the SACR register */ 56cc708597SJiafei Pan bl _set_smmu_pagesz_64 57cc708597SJiafei Pan#endif 58cc708597SJiafei Pan1: 59cc708597SJiafei Pan /* 60cc708597SJiafei Pan * May be cntfrq_el0 needs to be assigned 61cc708597SJiafei Pan * the value COUNTER_FREQUENCY 62cc708597SJiafei Pan */ 63cc708597SJiafei Pan mov x30, x29 64cc708597SJiafei Pan ret 65cc708597SJiafei Panendfunc plat_reset_handler 66cc708597SJiafei Pan 67cc708597SJiafei Pan/* 68cc708597SJiafei Pan * void plat_secondary_cold_boot_setup (void); 69cc708597SJiafei Pan * 70cc708597SJiafei Pan * This function performs any platform specific actions 71cc708597SJiafei Pan * needed for a secondary cpu after a cold reset e.g 72cc708597SJiafei Pan * mark the cpu's presence, mechanism to place it in a 73cc708597SJiafei Pan * holding pen etc. 74cc708597SJiafei Pan */ 75cc708597SJiafei Panfunc plat_secondary_cold_boot_setup 76cc708597SJiafei Pan /* ls1046a does not do cold boot for secondary CPU */ 77cc708597SJiafei Pancb_panic: 78cc708597SJiafei Pan b cb_panic 79cc708597SJiafei Panendfunc plat_secondary_cold_boot_setup 80cc708597SJiafei Pan 81cc708597SJiafei Pan/* 82cc708597SJiafei Pan * unsigned int plat_is_my_cpu_primary (void); 83cc708597SJiafei Pan * 84cc708597SJiafei Pan * Find out whether the current cpu is the primary cpu. 85cc708597SJiafei Pan */ 86cc708597SJiafei Panfunc plat_is_my_cpu_primary 87cc708597SJiafei Pan mrs x0, mpidr_el1 88cc708597SJiafei Pan and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 89cc708597SJiafei Pan cmp x0, 0x0 90cc708597SJiafei Pan cset w0, eq 91cc708597SJiafei Pan ret 92cc708597SJiafei Panendfunc plat_is_my_cpu_primary 93