1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <caam.h> 11 #include <cassert.h> 12 #include <cci.h> 13 #include <common/debug.h> 14 #include <dcfg.h> 15 #ifdef I2C_INIT 16 #include <i2c.h> 17 #endif 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <ls_interconnect.h> 21 #ifdef POLICY_FUSE_PROVISION 22 #include <nxp_gpio.h> 23 #endif 24 #include <nxp_smmu.h> 25 #include <nxp_timer.h> 26 #include <plat_console.h> 27 #include <plat_gic.h> 28 #include <plat_tzc380.h> 29 #include <scfg.h> 30 #if defined(NXP_SFP_ENABLED) 31 #include <sfp.h> 32 #endif 33 34 #include <errata.h> 35 #include <ns_access.h> 36 #ifdef CONFIG_OCRAM_ECC_EN 37 #include <ocram.h> 38 #endif 39 #include <plat_common.h> 40 #include <platform_def.h> 41 #include <soc.h> 42 43 static dcfg_init_info_t dcfg_init_data = { 44 .g_nxp_dcfg_addr = NXP_DCFG_ADDR, 45 .nxp_sysclk_freq = NXP_SYSCLK_FREQ, 46 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ, 47 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, 48 }; 49 50 51 /* Function to return the SoC SYS CLK */ 52 unsigned int get_sys_clk(void) 53 { 54 return NXP_SYSCLK_FREQ; 55 } 56 57 /* 58 * Function returns the base counter frequency 59 * after reading the first entry at CNTFID0 (0x20 offset). 60 * 61 * Function is used by: 62 * 1. ARM common code for PSCI management. 63 * 2. ARM Generic Timer init. 64 * 65 */ 66 unsigned int plat_get_syscnt_freq2(void) 67 { 68 unsigned int counter_base_frequency; 69 70 counter_base_frequency = get_sys_clk()/4; 71 72 return counter_base_frequency; 73 } 74 75 #ifdef IMAGE_BL2 76 77 static struct soc_type soc_list[] = { 78 SOC_ENTRY(LS1023A, LS1023A, 1, 2), 79 SOC_ENTRY(LS1023AE, LS1023AE, 1, 2), 80 SOC_ENTRY(LS1023A_P23, LS1023A_P23, 1, 2), 81 SOC_ENTRY(LS1023AE_P23, LS1023AE_P23, 1, 2), 82 SOC_ENTRY(LS1043A, LS1043A, 1, 4), 83 SOC_ENTRY(LS1043AE, LS1043AE, 1, 4), 84 SOC_ENTRY(LS1043A_P23, LS1043A_P23, 1, 4), 85 SOC_ENTRY(LS1043AE_P23, LS1043AE_P23, 1, 4), 86 }; 87 88 #ifdef POLICY_FUSE_PROVISION 89 static gpio_init_info_t gpio_init_data = { 90 .gpio1_base_addr = NXP_GPIO1_ADDR, 91 .gpio2_base_addr = NXP_GPIO2_ADDR, 92 .gpio3_base_addr = NXP_GPIO3_ADDR, 93 .gpio4_base_addr = NXP_GPIO4_ADDR, 94 }; 95 #endif 96 97 /* 98 * Function to set the base counter frequency at 99 * the first entry of the Frequency Mode Table, 100 * at CNTFID0 (0x20 offset). 101 * 102 * Set the value of the pirmary core register cntfrq_el0. 103 */ 104 static void set_base_freq_CNTFID0(void) 105 { 106 /* 107 * Below register specifies the base frequency of the system counter. 108 * As per NXP Board Manuals: 109 * The system counter always works with SYS_REF_CLK/4 frequency clock. 110 * 111 */ 112 unsigned int counter_base_frequency = get_sys_clk()/4; 113 114 /* 115 * Setting the frequency in the Frequency modes table. 116 * 117 * Note: The value for ls1046ardb board at this offset 118 * is not RW as stated. This offset have the 119 * fixed value of 100000400 Hz. 120 * 121 * The below code line has no effect. 122 * Keeping it for other platforms where it has effect. 123 */ 124 mmio_write_32(NXP_TIMER_ADDR + CNTFID_OFF, counter_base_frequency); 125 126 write_cntfrq_el0(counter_base_frequency); 127 } 128 129 void soc_preload_setup(void) 130 { 131 132 } 133 134 /******************************************************************************* 135 * This function implements soc specific erratas 136 * This is called before DDR is initialized or MMU is enabled 137 ******************************************************************************/ 138 void soc_early_init(void) 139 { 140 uint8_t num_clusters, cores_per_cluster; 141 dram_regions_info_t *dram_regions_info = get_dram_regions_info(); 142 143 #ifdef CONFIG_OCRAM_ECC_EN 144 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE); 145 #endif 146 dcfg_init(&dcfg_init_data); 147 #ifdef POLICY_FUSE_PROVISION 148 gpio_init(&gpio_init_data); 149 sec_init(NXP_CAAM_ADDR); 150 #endif 151 #if LOG_LEVEL > 0 152 /* Initialize the console to provide early debug support */ 153 154 plat_console_init(NXP_CONSOLE_ADDR, 155 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 156 #endif 157 set_base_freq_CNTFID0(); 158 159 /* Enable snooping on SEC read and write transactions */ 160 scfg_setbits32((void *)(NXP_SCFG_ADDR + SCFG_SNPCNFGCR_OFFSET), 161 SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP); 162 163 /* 164 * Initialize Interconnect for this cluster during cold boot. 165 * No need for locks as no other CPU is active. 166 */ 167 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 168 169 /* 170 * Enable Interconnect coherency for the primary CPU's cluster. 171 */ 172 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 173 plat_ls_interconnect_enter_coherency(num_clusters); 174 175 /* 176 * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts. 177 */ 178 smmu_cache_unlock(NXP_SMMU_ADDR); 179 INFO("SMMU Cache Unlocking is Configured.\n"); 180 181 #if TRUSTED_BOARD_BOOT 182 uint32_t mode; 183 184 sfp_init(NXP_SFP_ADDR); 185 /* 186 * For secure boot disable SMMU. 187 * Later when platform security policy comes in picture, 188 * this might get modified based on the policy 189 */ 190 if (check_boot_mode_secure(&mode) == true) { 191 bypass_smmu(NXP_SMMU_ADDR); 192 } 193 194 /* 195 * For Mbedtls currently crypto is not supported via CAAM 196 * enable it when that support is there. In tbbr.mk 197 * the CAAM_INTEG is set as 0. 198 */ 199 200 #ifndef MBEDTLS_X509 201 /* Initialize the crypto accelerator if enabled */ 202 if (is_sec_enabled() == false) { 203 INFO("SEC is disabled.\n"); 204 } else { 205 sec_init(NXP_CAAM_ADDR); 206 } 207 #endif 208 #elif defined(POLICY_FUSE_PROVISION) 209 gpio_init(&gpio_init_data); 210 sfp_init(NXP_SFP_ADDR); 211 sec_init(NXP_CAAM_ADDR); 212 #endif 213 214 soc_errata(); 215 216 /* 217 * Initialize system level generic timer for Layerscape Socs. 218 */ 219 delay_timer_init(NXP_TIMER_ADDR); 220 221 #ifdef DDR_INIT 222 i2c_init(NXP_I2C_ADDR); 223 dram_regions_info->total_dram_size = init_ddr(); 224 #endif 225 } 226 227 void soc_bl2_prepare_exit(void) 228 { 229 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) 230 set_sfp_wr_disable(); 231 #endif 232 } 233 234 /***************************************************************************** 235 * This function returns the boot device based on RCW_SRC 236 ****************************************************************************/ 237 enum boot_device get_boot_dev(void) 238 { 239 enum boot_device src = BOOT_DEVICE_NONE; 240 uint32_t porsr1; 241 uint32_t rcw_src, val; 242 243 porsr1 = read_reg_porsr1(); 244 245 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; 246 247 val = rcw_src & RCW_SRC_NAND_MASK; 248 249 if (val == RCW_SRC_NAND_VAL) { 250 val = rcw_src & NAND_RESERVED_MASK; 251 if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) { 252 src = BOOT_DEVICE_IFC_NAND; 253 INFO("RCW BOOT SRC is IFC NAND\n"); 254 } 255 } else { 256 /* RCW SRC NOR */ 257 val = rcw_src & RCW_SRC_NOR_MASK; 258 if (val == NOR_8B_VAL || val == NOR_16B_VAL) { 259 src = BOOT_DEVICE_IFC_NOR; 260 INFO("RCW BOOT SRC is IFC NOR\n"); 261 } else { 262 switch (rcw_src) { 263 case QSPI_VAL1: 264 case QSPI_VAL2: 265 src = BOOT_DEVICE_QSPI; 266 INFO("RCW BOOT SRC is QSPI\n"); 267 break; 268 case SD_VAL: 269 src = BOOT_DEVICE_EMMC; 270 INFO("RCW BOOT SRC is SD/EMMC\n"); 271 break; 272 default: 273 src = BOOT_DEVICE_NONE; 274 } 275 } 276 } 277 278 return src; 279 } 280 281 /* This function sets up access permissions on memory regions */ 282 void soc_mem_access(void) 283 { 284 struct tzc380_reg tzc380_reg_list[MAX_NUM_TZC_REGION]; 285 int dram_idx, index = 0U; 286 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 287 288 for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions; 289 dram_idx++) { 290 if (info_dram_regions->region[dram_idx].size == 0) { 291 ERROR("DDR init failure, or"); 292 ERROR("DRAM regions not populated correctly.\n"); 293 break; 294 } 295 296 index = populate_tzc380_reg_list(tzc380_reg_list, 297 dram_idx, index, 298 info_dram_regions->region[dram_idx].addr, 299 info_dram_regions->region[dram_idx].size, 300 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 301 } 302 303 mem_access_setup(NXP_TZC_ADDR, index, tzc380_reg_list); 304 305 /* Configure CSU secure access register to disable TZASC bypass mux */ 306 mmio_write_32((uintptr_t)(NXP_CSU_ADDR + 307 CSU_SEC_ACCESS_REG_OFFSET), 308 bswap32(TZASC_BYPASS_MUX_DISABLE)); 309 } 310 311 312 #else 313 const unsigned char _power_domain_tree_desc[] = {1, 1, 4}; 314 315 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, 316 assert_invalid_ls1043_cluster_count); 317 318 /* This function returns the SoC topology */ 319 const unsigned char *plat_get_power_domain_tree_desc(void) 320 { 321 322 return _power_domain_tree_desc; 323 } 324 325 /* 326 * This function returns the core count within the cluster corresponding to 327 * `mpidr`. 328 */ 329 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) 330 { 331 return CORES_PER_CLUSTER; 332 } 333 334 void soc_early_platform_setup2(void) 335 { 336 dcfg_init(&dcfg_init_data); 337 /* Initialize system level generic timer for Socs */ 338 delay_timer_init(NXP_TIMER_ADDR); 339 340 #if LOG_LEVEL > 0 341 /* Initialize the console to provide early debug support */ 342 plat_console_init(NXP_CONSOLE_ADDR, 343 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 344 #endif 345 } 346 347 /* 348 * For LS1043a rev1.0, GIC base address align with 4k. 349 * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT] 350 * is set, GIC base address align with 4K, or else align 351 * with 64k. 352 */ 353 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base) 354 { 355 uint32_t *ccsr_svr = (uint32_t *)(NXP_DCFG_ADDR + DCFG_SVR_OFFSET); 356 uint32_t *gic_align = (uint32_t *)(NXP_SCFG_ADDR + 357 SCFG_GIC400_ADDR_ALIGN_OFFSET); 358 uint32_t val; 359 360 val = be32toh(mmio_read_32((uintptr_t)ccsr_svr)); 361 362 if ((val & 0xff) == REV1_1) { 363 val = be32toh(mmio_read_32((uintptr_t)gic_align)); 364 if (val & (1L << GIC_ADDR_BIT)) { 365 *gicc_base = NXP_GICC_4K_ADDR; 366 *gicd_base = NXP_GICD_4K_ADDR; 367 } else { 368 *gicc_base = NXP_GICC_64K_ADDR; 369 *gicd_base = NXP_GICD_64K_ADDR; 370 } 371 } else { 372 *gicc_base = NXP_GICC_4K_ADDR; 373 *gicd_base = NXP_GICD_4K_ADDR; 374 } 375 } 376 377 void soc_platform_setup(void) 378 { 379 /* Initialize the GIC driver, cpu and distributor interfaces */ 380 static uint32_t target_mask_array[PLATFORM_CORE_COUNT]; 381 /* 382 * On a GICv2 system, the Group 1 secure interrupts are treated 383 * as Group 0 interrupts. 384 */ 385 static interrupt_prop_t ls_interrupt_props[] = { 386 PLAT_LS_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 387 PLAT_LS_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 388 }; 389 static uint32_t gicc_base, gicd_base; 390 391 get_gic_offset(&gicc_base, &gicd_base); 392 plat_ls_gic_driver_init(gicd_base, gicc_base, 393 PLATFORM_CORE_COUNT, 394 ls_interrupt_props, 395 ARRAY_SIZE(ls_interrupt_props), 396 target_mask_array); 397 398 plat_ls_gic_init(); 399 enable_init_timer(); 400 } 401 402 /* This function initializes the soc from the BL31 module */ 403 void soc_init(void) 404 { 405 /* low-level init of the soc */ 406 soc_init_lowlevel(); 407 _init_global_data(); 408 soc_init_percpu(); 409 _initialize_psci(); 410 411 /* 412 * Initialize the interconnect during cold boot. 413 * No need for locks as no other CPU is active. 414 */ 415 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 416 417 /* 418 * Enable coherency in interconnect for the primary CPU's cluster. 419 * Earlier bootloader stages might already do this but we can't 420 * assume so. No harm in executing this code twice. 421 */ 422 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 423 424 /* Init CSU to enable non-secure access to peripherals */ 425 enable_layerscape_ns_access(ns_dev, ARRAY_SIZE(ns_dev), NXP_CSU_ADDR); 426 427 /* Initialize the crypto accelerator if enabled */ 428 if (is_sec_enabled() == false) { 429 INFO("SEC is disabled.\n"); 430 } else { 431 sec_init(NXP_CAAM_ADDR); 432 } 433 } 434 435 void soc_runtime_setup(void) 436 { 437 438 } 439 #endif 440