1 /* 2 * Copyright 2018-2021, 2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <caam.h> 11 #include <cassert.h> 12 #include <cci.h> 13 #include <common/debug.h> 14 #include <dcfg.h> 15 #ifdef I2C_INIT 16 #include <i2c.h> 17 #endif 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <ls_interconnect.h> 21 #ifdef POLICY_FUSE_PROVISION 22 #include <nxp_gpio.h> 23 #endif 24 #include <nxp_smmu.h> 25 #include <nxp_timer.h> 26 #include <plat_console.h> 27 #include <plat_gic.h> 28 #include <plat_tzc380.h> 29 #include <scfg.h> 30 #if defined(NXP_SFP_ENABLED) 31 #include <sfp.h> 32 #endif 33 #if TRUSTED_BOARD_BOOT 34 #include <snvs.h> 35 #endif 36 37 #include <errata.h> 38 #include <ns_access.h> 39 #ifdef CONFIG_OCRAM_ECC_EN 40 #include <ocram.h> 41 #endif 42 #include <plat_common.h> 43 #include <platform_def.h> 44 #include <soc.h> 45 46 static dcfg_init_info_t dcfg_init_data = { 47 .g_nxp_dcfg_addr = NXP_DCFG_ADDR, 48 .nxp_sysclk_freq = NXP_SYSCLK_FREQ, 49 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ, 50 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, 51 }; 52 53 54 /* Function to return the SoC SYS CLK */ 55 unsigned int get_sys_clk(void) 56 { 57 return NXP_SYSCLK_FREQ; 58 } 59 60 /* 61 * Function returns the base counter frequency 62 * after reading the first entry at CNTFID0 (0x20 offset). 63 * 64 * Function is used by: 65 * 1. ARM common code for PSCI management. 66 * 2. ARM Generic Timer init. 67 * 68 */ 69 unsigned int plat_get_syscnt_freq2(void) 70 { 71 unsigned int counter_base_frequency; 72 73 counter_base_frequency = get_sys_clk()/4; 74 75 return counter_base_frequency; 76 } 77 78 #ifdef IMAGE_BL2 79 80 static struct soc_type soc_list[] = { 81 SOC_ENTRY(LS1023A, LS1023A, 1, 2), 82 SOC_ENTRY(LS1023AE, LS1023AE, 1, 2), 83 SOC_ENTRY(LS1023A_P23, LS1023A_P23, 1, 2), 84 SOC_ENTRY(LS1023AE_P23, LS1023AE_P23, 1, 2), 85 SOC_ENTRY(LS1043A, LS1043A, 1, 4), 86 SOC_ENTRY(LS1043AE, LS1043AE, 1, 4), 87 SOC_ENTRY(LS1043A_P23, LS1043A_P23, 1, 4), 88 SOC_ENTRY(LS1043AE_P23, LS1043AE_P23, 1, 4), 89 }; 90 91 #ifdef POLICY_FUSE_PROVISION 92 static gpio_init_info_t gpio_init_data = { 93 .gpio1_base_addr = NXP_GPIO1_ADDR, 94 .gpio2_base_addr = NXP_GPIO2_ADDR, 95 .gpio3_base_addr = NXP_GPIO3_ADDR, 96 .gpio4_base_addr = NXP_GPIO4_ADDR, 97 }; 98 #endif 99 100 /* 101 * Function to set the base counter frequency at 102 * the first entry of the Frequency Mode Table, 103 * at CNTFID0 (0x20 offset). 104 * 105 * Set the value of the pirmary core register cntfrq_el0. 106 */ 107 static void set_base_freq_CNTFID0(void) 108 { 109 /* 110 * Below register specifies the base frequency of the system counter. 111 * As per NXP Board Manuals: 112 * The system counter always works with SYS_REF_CLK/4 frequency clock. 113 * 114 */ 115 unsigned int counter_base_frequency = get_sys_clk()/4; 116 117 /* 118 * Setting the frequency in the Frequency modes table. 119 * 120 * Note: The value for ls1046ardb board at this offset 121 * is not RW as stated. This offset have the 122 * fixed value of 100000400 Hz. 123 * 124 * The below code line has no effect. 125 * Keeping it for other platforms where it has effect. 126 */ 127 mmio_write_32(NXP_TIMER_ADDR + CNTFID_OFF, counter_base_frequency); 128 129 write_cntfrq_el0(counter_base_frequency); 130 } 131 132 void soc_preload_setup(void) 133 { 134 135 } 136 137 /******************************************************************************* 138 * This function implements soc specific erratas 139 * This is called before DDR is initialized or MMU is enabled 140 ******************************************************************************/ 141 void soc_early_init(void) 142 { 143 uint8_t num_clusters, cores_per_cluster; 144 dram_regions_info_t *dram_regions_info = get_dram_regions_info(); 145 146 #if TRUSTED_BOARD_BOOT 147 snvs_init(NXP_SNVS_ADDR); 148 #endif 149 150 #ifdef CONFIG_OCRAM_ECC_EN 151 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE); 152 #endif 153 dcfg_init(&dcfg_init_data); 154 #ifdef POLICY_FUSE_PROVISION 155 gpio_init(&gpio_init_data); 156 sec_init(NXP_CAAM_ADDR); 157 #endif 158 #if LOG_LEVEL > 0 159 /* Initialize the console to provide early debug support */ 160 161 plat_console_init(NXP_CONSOLE_ADDR, 162 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 163 #endif 164 set_base_freq_CNTFID0(); 165 166 /* Enable snooping on SEC read and write transactions */ 167 scfg_setbits32((void *)(NXP_SCFG_ADDR + SCFG_SNPCNFGCR_OFFSET), 168 SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP); 169 170 /* 171 * Initialize Interconnect for this cluster during cold boot. 172 * No need for locks as no other CPU is active. 173 */ 174 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 175 176 /* 177 * Enable Interconnect coherency for the primary CPU's cluster. 178 */ 179 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 180 plat_ls_interconnect_enter_coherency(num_clusters); 181 182 /* 183 * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts. 184 */ 185 smmu_cache_unlock(NXP_SMMU_ADDR); 186 INFO("SMMU Cache Unlocking is Configured.\n"); 187 188 #if TRUSTED_BOARD_BOOT 189 uint32_t mode; 190 191 sfp_init(NXP_SFP_ADDR); 192 /* 193 * For secure boot disable SMMU. 194 * Later when platform security policy comes in picture, 195 * this might get modified based on the policy 196 */ 197 if (check_boot_mode_secure(&mode) == true) { 198 bypass_smmu(NXP_SMMU_ADDR); 199 } 200 201 /* 202 * For Mbedtls currently crypto is not supported via CAAM 203 * enable it when that support is there. In tbbr.mk 204 * the CAAM_INTEG is set as 0. 205 */ 206 207 #ifndef MBEDTLS_X509 208 /* Initialize the crypto accelerator if enabled */ 209 if (is_sec_enabled() == false) { 210 INFO("SEC is disabled.\n"); 211 } else { 212 sec_init(NXP_CAAM_ADDR); 213 } 214 #endif 215 #elif defined(POLICY_FUSE_PROVISION) 216 gpio_init(&gpio_init_data); 217 sfp_init(NXP_SFP_ADDR); 218 sec_init(NXP_CAAM_ADDR); 219 #endif 220 221 soc_errata(); 222 223 /* 224 * Initialize system level generic timer for Layerscape Socs. 225 */ 226 delay_timer_init(NXP_TIMER_ADDR); 227 228 #ifdef DDR_INIT 229 i2c_init(NXP_I2C_ADDR); 230 dram_regions_info->total_dram_size = init_ddr(); 231 #endif 232 } 233 234 void soc_bl2_prepare_exit(void) 235 { 236 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) 237 set_sfp_wr_disable(); 238 #endif 239 } 240 241 /***************************************************************************** 242 * This function returns the boot device based on RCW_SRC 243 ****************************************************************************/ 244 enum boot_device get_boot_dev(void) 245 { 246 enum boot_device src = BOOT_DEVICE_NONE; 247 uint32_t porsr1; 248 uint32_t rcw_src, val; 249 250 porsr1 = read_reg_porsr1(); 251 252 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; 253 254 val = rcw_src & RCW_SRC_NAND_MASK; 255 256 if (val == RCW_SRC_NAND_VAL) { 257 val = rcw_src & NAND_RESERVED_MASK; 258 if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) { 259 src = BOOT_DEVICE_IFC_NAND; 260 INFO("RCW BOOT SRC is IFC NAND\n"); 261 } 262 } else { 263 /* RCW SRC NOR */ 264 val = rcw_src & RCW_SRC_NOR_MASK; 265 if (val == NOR_8B_VAL || val == NOR_16B_VAL) { 266 src = BOOT_DEVICE_IFC_NOR; 267 INFO("RCW BOOT SRC is IFC NOR\n"); 268 } else { 269 switch (rcw_src) { 270 case QSPI_VAL1: 271 case QSPI_VAL2: 272 src = BOOT_DEVICE_QSPI; 273 INFO("RCW BOOT SRC is QSPI\n"); 274 break; 275 case SD_VAL: 276 src = BOOT_DEVICE_EMMC; 277 INFO("RCW BOOT SRC is SD/EMMC\n"); 278 break; 279 default: 280 src = BOOT_DEVICE_NONE; 281 } 282 } 283 } 284 285 return src; 286 } 287 288 /* This function sets up access permissions on memory regions */ 289 void soc_mem_access(void) 290 { 291 struct tzc380_reg tzc380_reg_list[MAX_NUM_TZC_REGION]; 292 int dram_idx, index = 0U; 293 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 294 295 for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions; 296 dram_idx++) { 297 if (info_dram_regions->region[dram_idx].size == 0) { 298 ERROR("DDR init failure, or"); 299 ERROR("DRAM regions not populated correctly.\n"); 300 break; 301 } 302 303 index = populate_tzc380_reg_list(tzc380_reg_list, 304 dram_idx, index, 305 info_dram_regions->region[dram_idx].addr, 306 info_dram_regions->region[dram_idx].size, 307 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 308 } 309 310 mem_access_setup(NXP_TZC_ADDR, index, tzc380_reg_list); 311 312 /* Configure CSU secure access register to disable TZASC bypass mux */ 313 mmio_write_32((uintptr_t)(NXP_CSU_ADDR + 314 CSU_SEC_ACCESS_REG_OFFSET), 315 bswap32(TZASC_BYPASS_MUX_DISABLE)); 316 } 317 318 319 #else 320 const unsigned char _power_domain_tree_desc[] = {1, 1, 4}; 321 322 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, 323 assert_invalid_ls1043_cluster_count); 324 325 /* This function returns the SoC topology */ 326 const unsigned char *plat_get_power_domain_tree_desc(void) 327 { 328 329 return _power_domain_tree_desc; 330 } 331 332 /* 333 * This function returns the core count within the cluster corresponding to 334 * `mpidr`. 335 */ 336 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) 337 { 338 return CORES_PER_CLUSTER; 339 } 340 341 void soc_early_platform_setup2(void) 342 { 343 dcfg_init(&dcfg_init_data); 344 /* Initialize system level generic timer for Socs */ 345 delay_timer_init(NXP_TIMER_ADDR); 346 347 #if LOG_LEVEL > 0 348 /* Initialize the console to provide early debug support */ 349 plat_console_init(NXP_CONSOLE_ADDR, 350 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 351 #endif 352 } 353 354 /* 355 * For LS1043a rev1.0, GIC base address align with 4k. 356 * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT] 357 * is set, GIC base address align with 4K, or else align 358 * with 64k. 359 */ 360 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base) 361 { 362 uint32_t *ccsr_svr = (uint32_t *)(NXP_DCFG_ADDR + DCFG_SVR_OFFSET); 363 uint32_t *gic_align = (uint32_t *)(NXP_SCFG_ADDR + 364 SCFG_GIC400_ADDR_ALIGN_OFFSET); 365 uint32_t val; 366 367 val = be32toh(mmio_read_32((uintptr_t)ccsr_svr)); 368 369 if ((val & 0xff) == REV1_1) { 370 val = be32toh(mmio_read_32((uintptr_t)gic_align)); 371 if (val & (1L << GIC_ADDR_BIT)) { 372 *gicc_base = NXP_GICC_4K_ADDR; 373 *gicd_base = NXP_GICD_4K_ADDR; 374 } else { 375 *gicc_base = NXP_GICC_64K_ADDR; 376 *gicd_base = NXP_GICD_64K_ADDR; 377 } 378 } else { 379 *gicc_base = NXP_GICC_4K_ADDR; 380 *gicd_base = NXP_GICD_4K_ADDR; 381 } 382 } 383 384 void soc_platform_setup(void) 385 { 386 /* Initialize the GIC driver, cpu and distributor interfaces */ 387 static uint32_t target_mask_array[PLATFORM_CORE_COUNT]; 388 /* 389 * On a GICv2 system, the Group 1 secure interrupts are treated 390 * as Group 0 interrupts. 391 */ 392 static interrupt_prop_t ls_interrupt_props[] = { 393 PLAT_LS_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 394 PLAT_LS_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 395 }; 396 static uint32_t gicc_base, gicd_base; 397 398 get_gic_offset(&gicc_base, &gicd_base); 399 plat_ls_gic_driver_init(gicd_base, gicc_base, 400 PLATFORM_CORE_COUNT, 401 ls_interrupt_props, 402 ARRAY_SIZE(ls_interrupt_props), 403 target_mask_array); 404 405 plat_ls_gic_init(); 406 enable_init_timer(); 407 } 408 409 /* This function initializes the soc from the BL31 module */ 410 void soc_init(void) 411 { 412 /* low-level init of the soc */ 413 soc_init_lowlevel(); 414 _init_global_data(); 415 soc_init_percpu(); 416 _initialize_psci(); 417 418 /* 419 * Initialize the interconnect during cold boot. 420 * No need for locks as no other CPU is active. 421 */ 422 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 423 424 /* 425 * Enable coherency in interconnect for the primary CPU's cluster. 426 * Earlier bootloader stages might already do this but we can't 427 * assume so. No harm in executing this code twice. 428 */ 429 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 430 431 /* Init CSU to enable non-secure access to peripherals */ 432 enable_layerscape_ns_access(ns_dev, ARRAY_SIZE(ns_dev), NXP_CSU_ADDR); 433 434 /* Initialize the crypto accelerator if enabled */ 435 if (is_sec_enabled() == false) { 436 INFO("SEC is disabled.\n"); 437 } else { 438 sec_init(NXP_CAAM_ADDR); 439 } 440 } 441 442 void soc_runtime_setup(void) 443 { 444 445 } 446 #endif 447