1*e4bd65feSJiafei Pan /* 2*e4bd65feSJiafei Pan * Copyright 2018-2021 NXP 3*e4bd65feSJiafei Pan * 4*e4bd65feSJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*e4bd65feSJiafei Pan */ 6*e4bd65feSJiafei Pan 7*e4bd65feSJiafei Pan #ifndef PLAT_DEF_H 8*e4bd65feSJiafei Pan #define PLAT_DEF_H 9*e4bd65feSJiafei Pan 10*e4bd65feSJiafei Pan #include <arch.h> 11*e4bd65feSJiafei Pan /* 12*e4bd65feSJiafei Pan * Required without TBBR. 13*e4bd65feSJiafei Pan * To include the defines for DDR PHY Images. 14*e4bd65feSJiafei Pan */ 15*e4bd65feSJiafei Pan #include <tbbr_img_def.h> 16*e4bd65feSJiafei Pan 17*e4bd65feSJiafei Pan #include "policy.h" 18*e4bd65feSJiafei Pan #include <soc.h> 19*e4bd65feSJiafei Pan 20*e4bd65feSJiafei Pan #define NXP_SPD_EEPROM0 0x51 21*e4bd65feSJiafei Pan 22*e4bd65feSJiafei Pan #define NXP_SYSCLK_FREQ 100000000 23*e4bd65feSJiafei Pan #define NXP_DDRCLK_FREQ 100000000 24*e4bd65feSJiafei Pan 25*e4bd65feSJiafei Pan /* UART related definition */ 26*e4bd65feSJiafei Pan #define NXP_CONSOLE_ADDR NXP_UART_ADDR 27*e4bd65feSJiafei Pan #define NXP_CONSOLE_BAUDRATE 115200 28*e4bd65feSJiafei Pan 29*e4bd65feSJiafei Pan /* Size of cacheable stacks */ 30*e4bd65feSJiafei Pan #if defined(IMAGE_BL2) 31*e4bd65feSJiafei Pan #if defined(TRUSTED_BOARD_BOOT) 32*e4bd65feSJiafei Pan #define PLATFORM_STACK_SIZE 0x2000 33*e4bd65feSJiafei Pan #else 34*e4bd65feSJiafei Pan #define PLATFORM_STACK_SIZE 0x1000 35*e4bd65feSJiafei Pan #endif 36*e4bd65feSJiafei Pan #elif defined(IMAGE_BL31) 37*e4bd65feSJiafei Pan #define PLATFORM_STACK_SIZE 0x1000 38*e4bd65feSJiafei Pan #endif 39*e4bd65feSJiafei Pan 40*e4bd65feSJiafei Pan /* SD block buffer */ 41*e4bd65feSJiafei Pan #define NXP_SD_BLOCK_BUF_SIZE (0x00100000) 42*e4bd65feSJiafei Pan #define NXP_SD_BLOCK_BUF_ADDR ULL(0x80000000) 43*e4bd65feSJiafei Pan 44*e4bd65feSJiafei Pan #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 45*e4bd65feSJiafei Pan 46*e4bd65feSJiafei Pan /* IO defines as needed by IO driver framework */ 47*e4bd65feSJiafei Pan #define MAX_IO_DEVICES 3 48*e4bd65feSJiafei Pan #define MAX_IO_BLOCK_DEVICES 1 49*e4bd65feSJiafei Pan #define MAX_IO_HANDLES 4 50*e4bd65feSJiafei Pan 51*e4bd65feSJiafei Pan /* 52*e4bd65feSJiafei Pan * FIP image defines - Offset at which FIP Image would be present 53*e4bd65feSJiafei Pan * Image would include Bl31 , Bl33 and Bl32 (optional) 54*e4bd65feSJiafei Pan */ 55*e4bd65feSJiafei Pan #ifdef POLICY_FUSE_PROVISION 56*e4bd65feSJiafei Pan #define MAX_FIP_DEVICES 2 57*e4bd65feSJiafei Pan #endif 58*e4bd65feSJiafei Pan 59*e4bd65feSJiafei Pan #ifndef MAX_FIP_DEVICES 60*e4bd65feSJiafei Pan #define MAX_FIP_DEVICES 1 61*e4bd65feSJiafei Pan #endif 62*e4bd65feSJiafei Pan 63*e4bd65feSJiafei Pan /* 64*e4bd65feSJiafei Pan * ID of the secure physical generic timer interrupt used by the BL32. 65*e4bd65feSJiafei Pan */ 66*e4bd65feSJiafei Pan #define BL32_IRQ_SEC_PHY_TIMER 29 67*e4bd65feSJiafei Pan 68*e4bd65feSJiafei Pan /* 69*e4bd65feSJiafei Pan * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 70*e4bd65feSJiafei Pan * terminology. On a GICv2 system or mode, the lists will be merged and treated 71*e4bd65feSJiafei Pan * as Group 0 interrupts. 72*e4bd65feSJiafei Pan */ 73*e4bd65feSJiafei Pan #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 74*e4bd65feSJiafei Pan INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 75*e4bd65feSJiafei Pan GIC_INTR_CFG_LEVEL) 76*e4bd65feSJiafei Pan 77*e4bd65feSJiafei Pan #define PLAT_LS_G0_IRQ_PROPS(grp) 78*e4bd65feSJiafei Pan 79*e4bd65feSJiafei Pan #endif /* PLAT_DEF_H */ 80