1*3b0de918SJiafei Pan/* 2*3b0de918SJiafei Pan * Copyright 2018-2021 NXP 3*3b0de918SJiafei Pan * 4*3b0de918SJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*3b0de918SJiafei Pan */ 6*3b0de918SJiafei Pan 7*3b0de918SJiafei Pan#include <arch.h> 8*3b0de918SJiafei Pan#include <asm_macros.S> 9*3b0de918SJiafei Pan 10*3b0de918SJiafei Pan#include <platform_def.h> 11*3b0de918SJiafei Pan 12*3b0de918SJiafei Pan .globl plat_secondary_cold_boot_setup 13*3b0de918SJiafei Pan .globl plat_is_my_cpu_primary 14*3b0de918SJiafei Pan .globl plat_reset_handler 15*3b0de918SJiafei Pan .globl platform_mem_init 16*3b0de918SJiafei Pan 17*3b0de918SJiafei Panfunc platform_mem1_init 18*3b0de918SJiafei Pan ret 19*3b0de918SJiafei Panendfunc platform_mem1_init 20*3b0de918SJiafei Pan 21*3b0de918SJiafei Panfunc platform_mem_init 22*3b0de918SJiafei Pan ret 23*3b0de918SJiafei Panendfunc platform_mem_init 24*3b0de918SJiafei Pan 25*3b0de918SJiafei Panfunc apply_platform_errata 26*3b0de918SJiafei Pan ret 27*3b0de918SJiafei Panendfunc apply_platform_errata 28*3b0de918SJiafei Pan 29*3b0de918SJiafei Panfunc plat_reset_handler 30*3b0de918SJiafei Pan mov x29, x30 31*3b0de918SJiafei Pan bl apply_platform_errata 32*3b0de918SJiafei Pan 33*3b0de918SJiafei Pan#if defined(IMAGE_BL31) 34*3b0de918SJiafei Pan ldr x0, =POLICY_SMMU_PAGESZ_64K 35*3b0de918SJiafei Pan cbz x0, 1f 36*3b0de918SJiafei Pan /* Set the SMMU page size in the sACR register */ 37*3b0de918SJiafei Pan bl _set_smmu_pagesz_64 38*3b0de918SJiafei Pan#endif 39*3b0de918SJiafei Pan1: 40*3b0de918SJiafei Pan mov x30, x29 41*3b0de918SJiafei Pan ret 42*3b0de918SJiafei Panendfunc plat_reset_handler 43*3b0de918SJiafei Pan 44*3b0de918SJiafei Pan/* 45*3b0de918SJiafei Pan * void plat_secondary_cold_boot_setup (void); 46*3b0de918SJiafei Pan * 47*3b0de918SJiafei Pan * This function performs any platform specific actions 48*3b0de918SJiafei Pan * needed for a secondary cpu after a cold reset e.g 49*3b0de918SJiafei Pan * mark the cpu's presence, mechanism to place it in a 50*3b0de918SJiafei Pan * holding pen etc. 51*3b0de918SJiafei Pan */ 52*3b0de918SJiafei Panfunc plat_secondary_cold_boot_setup 53*3b0de918SJiafei Pan /* ls1043a does not do cold boot for secondary CPU */ 54*3b0de918SJiafei Pancb_panic: 55*3b0de918SJiafei Pan b cb_panic 56*3b0de918SJiafei Panendfunc plat_secondary_cold_boot_setup 57*3b0de918SJiafei Pan 58*3b0de918SJiafei Pan/* 59*3b0de918SJiafei Pan * unsigned int plat_is_my_cpu_primary (void); 60*3b0de918SJiafei Pan * 61*3b0de918SJiafei Pan * Find out whether the current cpu is the primary 62*3b0de918SJiafei Pan * cpu. 63*3b0de918SJiafei Pan */ 64*3b0de918SJiafei Panfunc plat_is_my_cpu_primary 65*3b0de918SJiafei Pan mrs x0, mpidr_el1 66*3b0de918SJiafei Pan and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 67*3b0de918SJiafei Pan cmp x0, 0x0 68*3b0de918SJiafei Pan cset w0, eq 69*3b0de918SJiafei Pan ret 70*3b0de918SJiafei Panendfunc plat_is_my_cpu_primary 71