1*9d250f03SJiafei Pan# 2*9d250f03SJiafei Pan# Copyright 2018-2021 NXP 3*9d250f03SJiafei Pan# 4*9d250f03SJiafei Pan# SPDX-License-Identifier: BSD-3-Clause 5*9d250f03SJiafei Pan# 6*9d250f03SJiafei Pan# 7*9d250f03SJiafei Pan#------------------------------------------------------------------------------ 8*9d250f03SJiafei Pan# 9*9d250f03SJiafei Pan# This file contains the basic architecture definitions that drive the build 10*9d250f03SJiafei Pan# 11*9d250f03SJiafei Pan# ----------------------------------------------------------------------------- 12*9d250f03SJiafei Pan 13*9d250f03SJiafei PanCORE_TYPE := a72 14*9d250f03SJiafei Pan 15*9d250f03SJiafei PanCACHE_LINE := 6 16*9d250f03SJiafei Pan 17*9d250f03SJiafei Pan# Set to GIC400 or GIC500 18*9d250f03SJiafei PanGIC := GIC500 19*9d250f03SJiafei Pan 20*9d250f03SJiafei Pan# Set to CCI400 or CCN504 or CCN508 21*9d250f03SJiafei PanINTERCONNECT := CCI400 22*9d250f03SJiafei Pan 23*9d250f03SJiafei Pan# Layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 24*9d250f03SJiafei PanCHASSIS := 3_2 25*9d250f03SJiafei Pan 26*9d250f03SJiafei Pan# TZC used is TZC380 or TZC400 27*9d250f03SJiafei PanTZC_ID := TZC400 28*9d250f03SJiafei Pan 29*9d250f03SJiafei Pan# CONSOLE is NS16550 or PL011 30*9d250f03SJiafei PanCONSOLE := NS16550 31*9d250f03SJiafei Pan 32*9d250f03SJiafei Pan# DDR PHY generation to be used 33*9d250f03SJiafei PanPLAT_DDR_PHY := PHY_GEN1 34*9d250f03SJiafei Pan 35*9d250f03SJiafei PanPHYS_SYS := 64 36*9d250f03SJiafei Pan 37*9d250f03SJiafei Pan# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def 38*9d250f03SJiafei Pan# Input to CST create_hdr_esbc tool 39*9d250f03SJiafei PanCSF_HDR_SZ := 0x3000 40*9d250f03SJiafei Pan 41*9d250f03SJiafei Pan# In IMAGE_BL2, compile time flag for handling Cache coherency 42*9d250f03SJiafei Pan# with CAAM for BL2 running from OCRAM 43*9d250f03SJiafei PanSEC_MEM_NON_COHERENT := yes 44*9d250f03SJiafei Pan 45*9d250f03SJiafei Pan# OCRAM MAP for BL2 46*9d250f03SJiafei Pan# Before BL2 47*9d250f03SJiafei Pan# 0x18000000 - 0x18009fff -> Used by ROM code 48*9d250f03SJiafei Pan# 0x1800a000 - 0x1800dfff -> CSF header for BL2 49*9d250f03SJiafei Pan# For FlexSFlexSPI boot 50*9d250f03SJiafei Pan# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary 51*9d250f03SJiafei Pan# For SD boot 52*9d250f03SJiafei Pan# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary 53*9d250f03SJiafei Pan# 0x18030000 - 0x18040000 -> Reserved for SD buffer 54*9d250f03SJiafei PanOCRAM_START_ADDR := 0x18000000 55*9d250f03SJiafei PanOCRAM_SIZE := 0x40000 56*9d250f03SJiafei Pan 57*9d250f03SJiafei Pan# Area of OCRAM reserved by ROM code 58*9d250f03SJiafei PanNXP_ROM_RSVD := 0xa000 59*9d250f03SJiafei Pan 60*9d250f03SJiafei Pan# Location of BL2 on OCRAM 61*9d250f03SJiafei PanBL2_BASE_ADDR := $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) ))) 62*9d250f03SJiafei Pan 63*9d250f03SJiafei Pan# Covert to HEX to be used by create_pbl.mk 64*9d250f03SJiafei PanBL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc)) 65*9d250f03SJiafei Pan 66*9d250f03SJiafei Pan# BL2_HDR_LOC is at (BL2_BASE + NXP_ROM_RSVD) 67*9d250f03SJiafei Pan# This value BL2_HDR_LOC + CSF_HDR_SZ should not 68*9d250f03SJiafei Pan# overalp with BL2_BASE 69*9d250f03SJiafei Pan# Input to CST create_hdr_isbc tool 70*9d250f03SJiafei PanBL2_HDR_LOC := 0x1800A000 71*9d250f03SJiafei Pan 72*9d250f03SJiafei Pan# SoC ERRATAS to be enabled 73*9d250f03SJiafei PanERRATA_SOC_A008850 := 1 74*9d250f03SJiafei Pan 75*9d250f03SJiafei PanERRATA_DDR_A009803 := 1 76*9d250f03SJiafei PanERRATA_DDR_A009942 := 1 77*9d250f03SJiafei PanERRATA_DDR_A010165 := 1 78*9d250f03SJiafei Pan 79*9d250f03SJiafei Pan# Enable dynamic memory mapping 80*9d250f03SJiafei PanPLAT_XLAT_TABLES_DYNAMIC := 1 81*9d250f03SJiafei Pan 82*9d250f03SJiafei Pan# Define Endianness of each module 83*9d250f03SJiafei PanNXP_GUR_ENDIANNESS := LE 84*9d250f03SJiafei PanNXP_DDR_ENDIANNESS := LE 85*9d250f03SJiafei PanNXP_SEC_ENDIANNESS := LE 86*9d250f03SJiafei PanNXP_SFP_ENDIANNESS := LE 87*9d250f03SJiafei PanNXP_SNVS_ENDIANNESS := LE 88*9d250f03SJiafei PanNXP_ESDHC_ENDIANNESS := LE 89*9d250f03SJiafei PanNXP_QSPI_ENDIANNESS := LE 90*9d250f03SJiafei PanNXP_FSPI_ENDIANNESS := LE 91*9d250f03SJiafei Pan 92*9d250f03SJiafei PanNXP_SFP_VER := 3_4 93*9d250f03SJiafei Pan 94*9d250f03SJiafei Pan# OCRAM ECC Enabled 95*9d250f03SJiafei PanOCRAM_ECC_EN := yes 96