1*34e2112dSJiafei Pan /* 2*34e2112dSJiafei Pan * Copyright 2018-2021 NXP 3*34e2112dSJiafei Pan * 4*34e2112dSJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*34e2112dSJiafei Pan */ 6*34e2112dSJiafei Pan 7*34e2112dSJiafei Pan #ifndef PLAT_DEF_H 8*34e2112dSJiafei Pan #define PLAT_DEF_H 9*34e2112dSJiafei Pan 10*34e2112dSJiafei Pan #include <arch.h> 11*34e2112dSJiafei Pan #include <cortex_a72.h> 12*34e2112dSJiafei Pan /* 13*34e2112dSJiafei Pan * Required without TBBR. 14*34e2112dSJiafei Pan * To include the defines for DDR PHY 15*34e2112dSJiafei Pan * Images. 16*34e2112dSJiafei Pan */ 17*34e2112dSJiafei Pan #include <tbbr_img_def.h> 18*34e2112dSJiafei Pan 19*34e2112dSJiafei Pan #include <policy.h> 20*34e2112dSJiafei Pan #include <soc.h> 21*34e2112dSJiafei Pan 22*34e2112dSJiafei Pan 23*34e2112dSJiafei Pan #define NXP_SYSCLK_FREQ 100000000 24*34e2112dSJiafei Pan #define NXP_DDRCLK_FREQ 100000000 25*34e2112dSJiafei Pan 26*34e2112dSJiafei Pan /* UART related definition */ 27*34e2112dSJiafei Pan #define NXP_CONSOLE_ADDR NXP_UART_ADDR 28*34e2112dSJiafei Pan #define NXP_CONSOLE_BAUDRATE 115200 29*34e2112dSJiafei Pan 30*34e2112dSJiafei Pan #define NXP_SPD_EEPROM0 0x51 31*34e2112dSJiafei Pan 32*34e2112dSJiafei Pan /* Size of cacheable stacks */ 33*34e2112dSJiafei Pan #if defined(IMAGE_BL2) 34*34e2112dSJiafei Pan #if defined(TRUSTED_BOARD_BOOT) 35*34e2112dSJiafei Pan #define PLATFORM_STACK_SIZE 0x2000 36*34e2112dSJiafei Pan #else 37*34e2112dSJiafei Pan #define PLATFORM_STACK_SIZE 0x1000 38*34e2112dSJiafei Pan #endif 39*34e2112dSJiafei Pan #elif defined(IMAGE_BL31) 40*34e2112dSJiafei Pan #define PLATFORM_STACK_SIZE 0x1000 41*34e2112dSJiafei Pan #endif 42*34e2112dSJiafei Pan 43*34e2112dSJiafei Pan /* SD block buffer */ 44*34e2112dSJiafei Pan #define NXP_SD_BLOCK_BUF_SIZE (0xC000) 45*34e2112dSJiafei Pan 46*34e2112dSJiafei Pan #ifdef SD_BOOT 47*34e2112dSJiafei Pan #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ 48*34e2112dSJiafei Pan - NXP_SD_BLOCK_BUF_SIZE) 49*34e2112dSJiafei Pan #else 50*34e2112dSJiafei Pan #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) 51*34e2112dSJiafei Pan #endif 52*34e2112dSJiafei Pan #define BL2_TEXT_LIMIT (BL2_LIMIT) 53*34e2112dSJiafei Pan 54*34e2112dSJiafei Pan /* IO defines as needed by IO driver framework */ 55*34e2112dSJiafei Pan #define MAX_IO_DEVICES 4 56*34e2112dSJiafei Pan #define MAX_IO_BLOCK_DEVICES 1 57*34e2112dSJiafei Pan #define MAX_IO_HANDLES 4 58*34e2112dSJiafei Pan 59*34e2112dSJiafei Pan #define BL31_WDOG_SEC 89 60*34e2112dSJiafei Pan 61*34e2112dSJiafei Pan /* 62*34e2112dSJiafei Pan * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 63*34e2112dSJiafei Pan * terminology. On a GICv2 system or mode, the lists will be merged and treated 64*34e2112dSJiafei Pan * as Group 0 interrupts. 65*34e2112dSJiafei Pan */ 66*34e2112dSJiafei Pan #define PLAT_LS_G1S_IRQ_PROPS(grp) \ 67*34e2112dSJiafei Pan INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 68*34e2112dSJiafei Pan GIC_INTR_CFG_EDGE) 69*34e2112dSJiafei Pan 70*34e2112dSJiafei Pan /* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ 71*34e2112dSJiafei Pan #define PLAT_LS_G0_IRQ_PROPS(grp) \ 72*34e2112dSJiafei Pan INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 73*34e2112dSJiafei Pan GIC_INTR_CFG_EDGE), \ 74*34e2112dSJiafei Pan INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \ 75*34e2112dSJiafei Pan GIC_INTR_CFG_LEVEL) 76*34e2112dSJiafei Pan #endif /* PLAT_DEF_H */ 77