1*9d250f03SJiafei Pan/* 2*9d250f03SJiafei Pan * Copyright 2018-2021 NXP 3*9d250f03SJiafei Pan * 4*9d250f03SJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*9d250f03SJiafei Pan */ 6*9d250f03SJiafei Pan 7*9d250f03SJiafei Pan#include <arch.h> 8*9d250f03SJiafei Pan#include <asm_macros.S> 9*9d250f03SJiafei Pan 10*9d250f03SJiafei Pan#include <platform_def.h> 11*9d250f03SJiafei Pan 12*9d250f03SJiafei Pan.globl plat_secondary_cold_boot_setup 13*9d250f03SJiafei Pan.globl plat_is_my_cpu_primary 14*9d250f03SJiafei Pan.globl plat_reset_handler 15*9d250f03SJiafei Pan.globl platform_mem_init 16*9d250f03SJiafei Pan 17*9d250f03SJiafei Panfunc platform_mem1_init 18*9d250f03SJiafei Pan ret 19*9d250f03SJiafei Panendfunc platform_mem1_init 20*9d250f03SJiafei Pan 21*9d250f03SJiafei Panfunc platform_mem_init 22*9d250f03SJiafei Pan ret 23*9d250f03SJiafei Panendfunc platform_mem_init 24*9d250f03SJiafei Pan 25*9d250f03SJiafei Panfunc apply_platform_errata 26*9d250f03SJiafei Pan ret 27*9d250f03SJiafei Panendfunc apply_platform_errata 28*9d250f03SJiafei Pan 29*9d250f03SJiafei Panfunc plat_reset_handler 30*9d250f03SJiafei Pan mov x29, x30 31*9d250f03SJiafei Pan bl apply_platform_errata 32*9d250f03SJiafei Pan 33*9d250f03SJiafei Pan#if defined(IMAGE_BL31) 34*9d250f03SJiafei Pan ldr x0, =POLICY_SMMU_PAGESZ_64K 35*9d250f03SJiafei Pan cbz x0, 1f 36*9d250f03SJiafei Pan /* Set the SMMU page size in the sACR register */ 37*9d250f03SJiafei Pan bl _set_smmu_pagesz_64 38*9d250f03SJiafei Pan#endif 39*9d250f03SJiafei Pan1: 40*9d250f03SJiafei Pan mov x30, x29 41*9d250f03SJiafei Pan ret 42*9d250f03SJiafei Panendfunc plat_reset_handler 43*9d250f03SJiafei Pan 44*9d250f03SJiafei Pan/* 45*9d250f03SJiafei Pan * void plat_secondary_cold_boot_setup (void); 46*9d250f03SJiafei Pan * 47*9d250f03SJiafei Pan * This function performs any platform specific actions 48*9d250f03SJiafei Pan * needed for a secondary cpu after a cold reset e.g 49*9d250f03SJiafei Pan * mark the cpu's presence, mechanism to place it in a 50*9d250f03SJiafei Pan * holding pen etc. 51*9d250f03SJiafei Pan */ 52*9d250f03SJiafei Panfunc plat_secondary_cold_boot_setup 53*9d250f03SJiafei Pan /* ls1028a does not do cold boot for secondary CPU */ 54*9d250f03SJiafei Pancb_panic: 55*9d250f03SJiafei Pan b cb_panic 56*9d250f03SJiafei Panendfunc plat_secondary_cold_boot_setup 57*9d250f03SJiafei Pan 58*9d250f03SJiafei Pan/* 59*9d250f03SJiafei Pan * unsigned int plat_is_my_cpu_primary (void); 60*9d250f03SJiafei Pan * 61*9d250f03SJiafei Pan * Find out whether the current cpu is the primary 62*9d250f03SJiafei Pan * cpu. 63*9d250f03SJiafei Pan */ 64*9d250f03SJiafei Panfunc plat_is_my_cpu_primary 65*9d250f03SJiafei Pan mrs x0, mpidr_el1 66*9d250f03SJiafei Pan and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 67*9d250f03SJiafei Pan cmp x0, 0x0 68*9d250f03SJiafei Pan cset w0, eq 69*9d250f03SJiafei Pan ret 70*9d250f03SJiafei Panendfunc plat_is_my_cpu_primary 71