1/* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <asm_macros.S> 8#include <platform_def.h> 9 10#define S32G_NCORE_CAIU0_BASE_ADDR UL(0x50400000) 11#define S32G_NCORE_CAIUTC_OFF U(0x0) 12#define S32G_NCORE_CAIUTC_ISOLEN_SHIFT U(1) 13 14.globl plat_crash_console_flush 15.globl plat_crash_console_init 16.globl plat_crash_console_putc 17.globl plat_is_my_cpu_primary 18.globl plat_my_core_pos 19.globl plat_reset_handler 20.globl plat_secondary_cold_boot_setup 21.globl platform_mem_init 22.globl s32g2_core_pos_by_mpidr 23 24/* int plat_crash_console_init(void); */ 25func plat_crash_console_init 26 mov_imm x0, UART_BASE 27 mov_imm x1, UART_CLOCK_HZ 28 mov_imm x2, UART_BAUDRATE 29 b console_linflex_core_init 30endfunc plat_crash_console_init 31 32/* int plat_crash_console_putc(int); */ 33func plat_crash_console_putc 34 mov_imm x1, UART_BASE 35 b console_linflex_core_putc 36 ret 37endfunc plat_crash_console_putc 38 39/* void plat_crash_console_flush(void); */ 40func plat_crash_console_flush 41 mov_imm x0, UART_BASE 42 b console_linflex_core_flush 43 ret 44endfunc plat_crash_console_flush 45 46/** 47 * unsigned int s32g2_core_pos_by_mpidr(u_register_t mpidr); 48 * 49 * In: x0 - MPIDR_EL1 50 * Out: x0 51 * Clobber list: x0, x1 52 */ 53func s32g2_core_pos_by_mpidr 54 and x1, x0, #MPIDR_CPU_MASK 55 and x0, x0, #MPIDR_CLUSTER_MASK 56 lsr x0, x0, #MPIDR_AFF1_SHIFT 57 add x0, x1, x0, lsl #PLATFORM_MPIDR_CPU_MASK_BITS 58 ret 59endfunc s32g2_core_pos_by_mpidr 60 61/** 62 * unsigned int plat_my_core_pos(void); 63 * 64 * Out: x0 65 * Clobber list: x0, x1, x8 66 */ 67func plat_my_core_pos 68 mov x8, x30 69 mrs x0, mpidr_el1 70 bl s32g2_core_pos_by_mpidr 71 mov x30, x8 72 ret 73endfunc plat_my_core_pos 74 75/** 76 * unsigned int plat_is_my_cpu_primary(void); 77 * 78 * Clobber list: x0, x1, x7, x8 79 */ 80func plat_is_my_cpu_primary 81 mov x7, x30 82 bl plat_my_core_pos 83 cmp x0, #PLATFORM_PRIMARY_CPU 84 cset x0, eq 85 mov x30, x7 86 ret 87endfunc plat_is_my_cpu_primary 88 89 90/** 91 * void plat_secondary_cold_boot_setup (void); 92 */ 93func plat_secondary_cold_boot_setup 94 ret 95endfunc plat_secondary_cold_boot_setup 96 97/** 98 * void plat_reset_handler(void); 99 * 100 * Set the CAIUTC[IsolEn] bit for the primary A53 cluster. 101 * This is so cache invalidate operations from the early TF-A boot code 102 * won't cause Ncore to crash. 103 * 104 * Clobber list: x0, x1, x2 105 */ 106func plat_reset_handler 107 mov x0, #S32G_NCORE_CAIU0_BASE_ADDR 108 ldr w1, [x0, #S32G_NCORE_CAIUTC_OFF] 109 movz w2, #1 110 lsl w2, w2, #S32G_NCORE_CAIUTC_ISOLEN_SHIFT 111 orr w1, w1, w2 112 str w1, [x0, #S32G_NCORE_CAIUTC_OFF] 113 ret 114endfunc plat_reset_handler 115 116/* void platform_mem_init(void); */ 117func platform_mem_init 118 mov x10, x30 119 mov x0, #BL31_BASE 120 mov x1, #(BL31_LIMIT & 0xFFFFU) 121 movk x1, #(BL31_LIMIT >> 16), lsl #16 122 sub x1, x1, x0 123 bl zeromem 124 mov x0, #BL33_BASE 125 mov x1, #(BL33_LIMIT & 0xFFFFU) 126 movk x1, #(BL33_LIMIT >> 16), lsl #16 127 sub x1, x1, x0 128 bl zeromem 129 mov x30, x10 130 ret 131endfunc platform_mem_init 132 133