1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <drivers/arm/gicv3.h> 9 #include <lib/xlat_tables/xlat_tables_v2.h> 10 #include <plat/common/platform.h> 11 #include <plat_console.h> 12 13 #include <s32cc-bl-common.h> 14 15 static entry_point_info_t bl33_image_ep_info; 16 17 static unsigned int s32g2_mpidr_to_core_pos(unsigned long mpidr); 18 19 static uint32_t get_spsr_for_bl33_entry(void) 20 { 21 unsigned long mode = MODE_EL1; 22 uint32_t spsr; 23 24 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 25 26 return spsr; 27 } 28 29 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 30 u_register_t arg2, u_register_t arg3) 31 { 32 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 33 bl33_image_ep_info.pc = BL33_BASE; 34 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 35 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 36 } 37 38 void bl31_plat_arch_setup(void) 39 { 40 int ret; 41 42 ret = s32cc_bl_mmu_setup(); 43 if (ret != 0) { 44 panic(); 45 } 46 47 console_s32g2_register(); 48 } 49 50 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 51 { 52 return &bl33_image_ep_info; 53 } 54 55 static int mmap_gic(const gicv3_driver_data_t *gic_data) 56 { 57 size_t gicr_size; 58 int ret; 59 60 ret = mmap_add_dynamic_region(gic_data->gicd_base, 61 gic_data->gicd_base, 62 PAGE_SIZE_64KB, 63 MT_DEVICE | MT_RW | MT_SECURE); 64 if (ret != 0) { 65 return ret; 66 } 67 68 gicr_size = gicv3_redist_size(0x0U); 69 ret = mmap_add_dynamic_region(gic_data->gicr_base, 70 gic_data->gicr_base, 71 gicr_size * gic_data->rdistif_num, 72 MT_DEVICE | MT_RW | MT_SECURE); 73 if (ret != 0) { 74 return ret; 75 } 76 77 return 0; 78 } 79 80 void bl31_platform_setup(void) 81 { 82 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 83 static gicv3_driver_data_t plat_gic_data = { 84 .gicd_base = PLAT_GICD_BASE, 85 .gicr_base = PLAT_GICR_BASE, 86 .rdistif_num = PLATFORM_CORE_COUNT, 87 .rdistif_base_addrs = rdistif_base_addrs, 88 .mpidr_to_core_pos = s32g2_mpidr_to_core_pos, 89 }; 90 unsigned int pos = plat_my_core_pos(); 91 int ret; 92 93 ret = mmap_gic(&plat_gic_data); 94 if (ret != 0) { 95 panic(); 96 } 97 98 gicv3_driver_init(&plat_gic_data); 99 gicv3_distif_init(); 100 gicv3_rdistif_init(pos); 101 gicv3_cpuif_enable(pos); 102 } 103 104 static unsigned int s32g2_mpidr_to_core_pos(unsigned long mpidr) 105 { 106 int core; 107 108 core = plat_core_pos_by_mpidr(mpidr); 109 if (core < 0) { 110 return 0; 111 } 112 113 return (unsigned int)core; 114 } 115 116