1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <common/desc_image_load.h> 9 #include <lib/mmio.h> 10 #include <plat/common/platform.h> 11 #include <plat_console.h> 12 #include <s32cc-clk-drv.h> 13 #include <plat_io_storage.h> 14 15 #define SIUL2_PC09_MSCR UL(0x4009C2E4) 16 #define SIUL2_PC10_MSCR UL(0x4009C2E8) 17 #define SIUL2_PC10_LIN0_IMCR UL(0x4009CA40) 18 19 #define LIN0_TX_MSCR_CFG U(0x00214001) 20 #define LIN0_RX_MSCR_CFG U(0x00094000) 21 #define LIN0_RX_IMCR_CFG U(0x00000002) 22 23 struct bl_load_info *plat_get_bl_image_load_info(void) 24 { 25 return get_bl_load_info_from_mem_params_desc(); 26 } 27 28 struct bl_params *plat_get_next_bl_params(void) 29 { 30 return get_next_bl_params_from_mem_params_desc(); 31 } 32 33 void plat_flush_next_bl_params(void) 34 { 35 flush_bl_params_desc(); 36 } 37 38 void bl2_platform_setup(void) 39 { 40 } 41 42 static void linflex_config_pinctrl(void) 43 { 44 /* set PC09 - MSCR[41] - for UART0 TXD */ 45 mmio_write_32(SIUL2_PC09_MSCR, LIN0_TX_MSCR_CFG); 46 /* set PC10 - MSCR[42] - for UART0 RXD */ 47 mmio_write_32(SIUL2_PC10_MSCR, LIN0_RX_MSCR_CFG); 48 /* set PC10 - MSCR[512]/IMCR[0] - for UART0 RXD */ 49 mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG); 50 } 51 52 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 53 u_register_t arg2, u_register_t arg3) 54 { 55 int ret; 56 57 ret = s32cc_init_early_clks(); 58 if (ret != 0) { 59 panic(); 60 } 61 62 linflex_config_pinctrl(); 63 console_s32g2_register(); 64 65 plat_s32g2_io_setup(); 66 } 67 68 void bl2_el3_plat_arch_setup(void) 69 { 70 } 71 72