xref: /rk3399_ARM-atf/plat/nxp/common/soc_errata/errata_a010539.c (revision 2ea18c7df31f8239e1052f39cf26f1bb8c9d0c25) 
1*85bd0929SJiafei Pan /*
2*85bd0929SJiafei Pan  * Copyright 2022 NXP
3*85bd0929SJiafei Pan  *
4*85bd0929SJiafei Pan  * SPDX-License-Identifier: BSD-3-Clause
5*85bd0929SJiafei Pan  *
6*85bd0929SJiafei Pan  */
7*85bd0929SJiafei Pan 
8*85bd0929SJiafei Pan #include <mmio.h>
9*85bd0929SJiafei Pan 
10*85bd0929SJiafei Pan #include <plat_common.h>
11*85bd0929SJiafei Pan 
erratum_a010539(void)12*85bd0929SJiafei Pan void erratum_a010539(void)
13*85bd0929SJiafei Pan {
14*85bd0929SJiafei Pan 	if (get_boot_dev() == BOOT_DEVICE_QSPI) {
15*85bd0929SJiafei Pan 		unsigned int *porsr1 = (void *)(NXP_DCFG_ADDR +
16*85bd0929SJiafei Pan 				DCFG_PORSR1_OFFSET);
17*85bd0929SJiafei Pan 		uint32_t val;
18*85bd0929SJiafei Pan 
19*85bd0929SJiafei Pan 		val = (gur_in32(porsr1) & ~PORSR1_RCW_MASK);
20*85bd0929SJiafei Pan 		mmio_write_32((uint32_t)(NXP_DCSR_DCFG_ADDR +
21*85bd0929SJiafei Pan 				DCFG_DCSR_PORCR1_OFFSET), htobe32(val));
22*85bd0929SJiafei Pan 		/* Erratum need to set '1' to all bits for reserved SCFG register 0x1a8 */
23*85bd0929SJiafei Pan 		mmio_write_32((uint32_t)(NXP_SCFG_ADDR + 0x1a8),
24*85bd0929SJiafei Pan 				htobe32(0xffffffff));
25*85bd0929SJiafei Pan 	}
26*85bd0929SJiafei Pan }
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