1*3d14a30bSJiafei Pan /* 2*3d14a30bSJiafei Pan * Copyright 2021 NXP 3*3d14a30bSJiafei Pan * 4*3d14a30bSJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*3d14a30bSJiafei Pan * 6*3d14a30bSJiafei Pan */ 7*3d14a30bSJiafei Pan #include <cci.h> 8*3d14a30bSJiafei Pan #include <common/debug.h> 9*3d14a30bSJiafei Pan #include <ls_interconnect.h> 10*3d14a30bSJiafei Pan #include <mmio.h> 11*3d14a30bSJiafei Pan 12*3d14a30bSJiafei Pan #include <platform_def.h> 13*3d14a30bSJiafei Pan erratum_a008850_early(void)14*3d14a30bSJiafei Panvoid erratum_a008850_early(void) 15*3d14a30bSJiafei Pan { 16*3d14a30bSJiafei Pan /* part 1 of 2 */ 17*3d14a30bSJiafei Pan uintptr_t cci_base = NXP_CCI_ADDR; 18*3d14a30bSJiafei Pan uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG); 19*3d14a30bSJiafei Pan 20*3d14a30bSJiafei Pan /* enabling forced barrier termination on CCI400 */ 21*3d14a30bSJiafei Pan mmio_write_32(cci_base + CTRL_OVERRIDE_REG, 22*3d14a30bSJiafei Pan (val | CCI_TERMINATE_BARRIER_TX)); 23*3d14a30bSJiafei Pan 24*3d14a30bSJiafei Pan } 25*3d14a30bSJiafei Pan erratum_a008850_post(void)26*3d14a30bSJiafei Panvoid erratum_a008850_post(void) 27*3d14a30bSJiafei Pan { 28*3d14a30bSJiafei Pan /* part 2 of 2 */ 29*3d14a30bSJiafei Pan uintptr_t cci_base = NXP_CCI_ADDR; 30*3d14a30bSJiafei Pan uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG); 31*3d14a30bSJiafei Pan 32*3d14a30bSJiafei Pan /* Clear the BARRIER_TX bit */ 33*3d14a30bSJiafei Pan val = val & ~(CCI_TERMINATE_BARRIER_TX); 34*3d14a30bSJiafei Pan 35*3d14a30bSJiafei Pan /* 36*3d14a30bSJiafei Pan * Disable barrier termination on CCI400, allowing 37*3d14a30bSJiafei Pan * barriers to propagate across CCI 38*3d14a30bSJiafei Pan */ 39*3d14a30bSJiafei Pan mmio_write_32(cci_base + CTRL_OVERRIDE_REG, val); 40*3d14a30bSJiafei Pan 41*3d14a30bSJiafei Pan INFO("SoC workaround for Errata A008850 Post-Phase was applied\n"); 42*3d14a30bSJiafei Pan } 43