1 /* 2 * Copyright 2018-2020 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #include <assert.h> 9 #include <inttypes.h> 10 #include <stdint.h> 11 12 #ifdef LS_EL3_INTERRUPT_HANDLER 13 #include <ls_interrupt_mgmt.h> 14 #endif 15 #include <mmu_def.h> 16 #include <plat_common.h> 17 18 /* 19 * Placeholder variables for copying the arguments that have been passed to 20 * BL31 from BL2. 21 */ 22 #ifdef TEST_BL31 23 #define SPSR_FOR_EL2H 0x3C9 24 #define SPSR_FOR_EL1H 0x3C5 25 #else 26 static entry_point_info_t bl31_image_ep_info; 27 #endif 28 29 static entry_point_info_t bl32_image_ep_info; 30 static entry_point_info_t bl33_image_ep_info; 31 32 static dram_regions_info_t dram_regions_info = {0}; 33 static uint64_t rcw_porsr1; 34 35 /* Return the pointer to the 'dram_regions_info structure of the DRAM. 36 * This structure is populated after init_ddr(). 37 */ 38 dram_regions_info_t *get_dram_regions_info(void) 39 { 40 return &dram_regions_info; 41 } 42 43 /* Return the RCW.PORSR1 value which was passed in from BL2 44 */ 45 uint64_t bl31_get_porsr1(void) 46 { 47 return rcw_porsr1; 48 } 49 50 /* 51 * Return pointer to the 'entry_point_info' structure of the next image for the 52 * security state specified: 53 * - BL33 corresponds to the non-secure image type; while 54 * - BL32 corresponds to the secure image type. 55 * - A NULL pointer is returned, if the image does not exist. 56 */ 57 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 58 { 59 entry_point_info_t *next_image_info; 60 61 assert(sec_state_is_valid(type)); 62 next_image_info = (type == NON_SECURE) 63 ? &bl33_image_ep_info : &bl32_image_ep_info; 64 65 #ifdef TEST_BL31 66 next_image_info->pc = _get_test_entry(); 67 next_image_info->spsr = SPSR_FOR_EL2H; 68 next_image_info->h.attr = NON_SECURE; 69 #endif 70 71 if (next_image_info->pc != 0U) { 72 return next_image_info; 73 } else { 74 return NULL; 75 } 76 } 77 78 /* 79 * Perform any BL31 early platform setup common to NXP platforms. 80 * - Here is an opportunity to copy parameters passed by the calling EL (S-EL1 81 * in BL2 & S-EL3 in BL1) before they are lost (potentially). 82 * - This needs to be done before the MMU is initialized so that the 83 * memory layout can be used while creating page tables. 84 * - BL2 has flushed this information to memory, in order to fetch latest data. 85 */ 86 87 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 88 u_register_t arg2, u_register_t arg3) 89 { 90 #ifndef TEST_BL31 91 int i = 0; 92 void *from_bl2 = (void *)arg0; 93 #endif 94 soc_early_platform_setup2(); 95 96 #ifdef TEST_BL31 97 dram_regions_info.num_dram_regions = 2; 98 dram_regions_info.total_dram_size = 0x100000000; 99 dram_regions_info.region[0].addr = 0x80000000; 100 dram_regions_info.region[0].size = 0x80000000; 101 dram_regions_info.region[1].addr = 0x880000000; 102 dram_regions_info.region[1].size = 0x80000000; 103 104 bl33_image_ep_info.pc = _get_test_entry(); 105 #else 106 /* 107 * Check params passed from BL2 should not be NULL, 108 */ 109 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 110 111 assert(params_from_bl2 != NULL); 112 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 113 assert(params_from_bl2->h.version >= VERSION_2); 114 115 bl_params_node_t *bl_params = params_from_bl2->head; 116 117 /* 118 * Copy BL33 and BL32 (if present), entry point information. 119 * They are stored in Secure RAM, in BL2's address space. 120 */ 121 while (bl_params != NULL) { 122 if (bl_params->image_id == BL31_IMAGE_ID) { 123 bl31_image_ep_info = *bl_params->ep_info; 124 dram_regions_info_t *loc_dram_regions_info = 125 (dram_regions_info_t *) bl31_image_ep_info.args.arg3; 126 127 dram_regions_info.num_dram_regions = 128 loc_dram_regions_info->num_dram_regions; 129 dram_regions_info.total_dram_size = 130 loc_dram_regions_info->total_dram_size; 131 VERBOSE("Number of DRAM Regions = %" PRIx64 "\n", 132 dram_regions_info.num_dram_regions); 133 134 for (i = 0; i < dram_regions_info.num_dram_regions; 135 i++) { 136 dram_regions_info.region[i].addr = 137 loc_dram_regions_info->region[i].addr; 138 dram_regions_info.region[i].size = 139 loc_dram_regions_info->region[i].size; 140 VERBOSE("DRAM%d Size = %" PRIx64 "\n", i, 141 dram_regions_info.region[i].size); 142 } 143 rcw_porsr1 = bl31_image_ep_info.args.arg4; 144 } 145 146 if (bl_params->image_id == BL32_IMAGE_ID) { 147 bl32_image_ep_info = *bl_params->ep_info; 148 } 149 150 if (bl_params->image_id == BL33_IMAGE_ID) { 151 bl33_image_ep_info = *bl_params->ep_info; 152 } 153 154 bl_params = bl_params->next_params_info; 155 } 156 #endif /* TEST_BL31 */ 157 158 if (bl33_image_ep_info.pc == 0) { 159 panic(); 160 } 161 162 /* 163 * perform basic initialization on the soc 164 */ 165 soc_init(); 166 } 167 168 /******************************************************************************* 169 * Perform any BL31 platform setup common to ARM standard platforms 170 ******************************************************************************/ 171 void bl31_platform_setup(void) 172 { 173 NOTICE("Welcome to %s BL31 Phase\n", BOARD); 174 soc_platform_setup(); 175 176 /* Console logs gone missing as part going to 177 * EL1 for initializing Bl32 if present. 178 * console flush is necessary to avoid it. 179 */ 180 (void)console_flush(); 181 } 182 183 void bl31_plat_runtime_setup(void) 184 { 185 #ifdef LS_EL3_INTERRUPT_HANDLER 186 ls_el3_interrupt_config(); 187 #endif 188 soc_runtime_setup(); 189 } 190 191 /******************************************************************************* 192 * Perform the very early platform specific architectural setup shared between 193 * ARM standard platforms. This only does basic initialization. Later 194 * architectural setup (bl31_arch_setup()) does not do anything platform 195 * specific. 196 ******************************************************************************/ 197 void bl31_plat_arch_setup(void) 198 { 199 200 ls_setup_page_tables(BL31_BASE, 201 BL31_END - BL31_BASE, 202 BL_CODE_BASE, 203 BL_CODE_END, 204 BL_RO_DATA_BASE, 205 BL_RO_DATA_END 206 #if USE_COHERENT_MEM 207 , BL_COHERENT_RAM_BASE, 208 BL_COHERENT_RAM_END 209 #endif 210 ); 211 enable_mmu_el3(0); 212 } 213