1*b53c2c5fSPankaj Gupta /* 2*b53c2c5fSPankaj Gupta * Copyright 2018-2020 NXP 3*b53c2c5fSPankaj Gupta * 4*b53c2c5fSPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*b53c2c5fSPankaj Gupta * 6*b53c2c5fSPankaj Gupta */ 7*b53c2c5fSPankaj Gupta 8*b53c2c5fSPankaj Gupta #ifndef MMU_MAP_DEF_H 9*b53c2c5fSPankaj Gupta #define MMU_MAP_DEF_H 10*b53c2c5fSPankaj Gupta 11*b53c2c5fSPankaj Gupta #include <lib/xlat_tables/xlat_tables_defs.h> 12*b53c2c5fSPankaj Gupta 13*b53c2c5fSPankaj Gupta #include <platform_def.h> 14*b53c2c5fSPankaj Gupta 15*b53c2c5fSPankaj Gupta 16*b53c2c5fSPankaj Gupta #define LS_MAP_CCSR MAP_REGION_FLAT(NXP_CCSR_ADDR, \ 17*b53c2c5fSPankaj Gupta NXP_CCSR_SIZE, \ 18*b53c2c5fSPankaj Gupta MT_DEVICE | MT_RW | MT_SECURE) 19*b53c2c5fSPankaj Gupta 20*b53c2c5fSPankaj Gupta #ifdef NXP_DCSR_ADDR 21*b53c2c5fSPankaj Gupta #define LS_MAP_DCSR MAP_REGION_FLAT(NXP_DCSR_ADDR, \ 22*b53c2c5fSPankaj Gupta NXP_DCSR_SIZE, \ 23*b53c2c5fSPankaj Gupta MT_DEVICE | MT_RW | MT_SECURE) 24*b53c2c5fSPankaj Gupta #endif 25*b53c2c5fSPankaj Gupta 26*b53c2c5fSPankaj Gupta #define LS_MAP_CONSOLE MAP_REGION_FLAT(NXP_DUART1_ADDR, \ 27*b53c2c5fSPankaj Gupta NXP_DUART_SIZE, \ 28*b53c2c5fSPankaj Gupta MT_DEVICE | MT_RW | MT_NS) 29*b53c2c5fSPankaj Gupta 30*b53c2c5fSPankaj Gupta #define LS_MAP_OCRAM MAP_REGION_FLAT(NXP_OCRAM_ADDR, \ 31*b53c2c5fSPankaj Gupta NXP_OCRAM_SIZE, \ 32*b53c2c5fSPankaj Gupta MT_DEVICE | MT_RW | MT_SECURE) 33*b53c2c5fSPankaj Gupta 34*b53c2c5fSPankaj Gupta #endif /* MMU_MAP_DEF_H */ 35