15d5c3ff3SJiafei Pan# Copyright 2020-2021 NXP 25d5c3ff3SJiafei Pan# 35d5c3ff3SJiafei Pan# SPDX-License-Identifier: BSD-3-Clause 45d5c3ff3SJiafei Pan# 55d5c3ff3SJiafei Pan 65d5c3ff3SJiafei Pan# Include build macros, for example: SET_NXP_MAKE_FLAG 75d5c3ff3SJiafei Paninclude plat/nxp/common/plat_make_helper/plat_build_macros.mk 85d5c3ff3SJiafei Pan 95d5c3ff3SJiafei Pan# Adding platform specific defines 105d5c3ff3SJiafei Pan 115d5c3ff3SJiafei Pan$(eval $(call add_define_val,BOARD,'"${BOARD}"')) 125d5c3ff3SJiafei Pan 135d5c3ff3SJiafei Panifeq (${POVDD_ENABLE},yes) 145d5c3ff3SJiafei Pan$(eval $(call add_define,CONFIG_POVDD_ENABLE)) 155d5c3ff3SJiafei Panendif 165d5c3ff3SJiafei Pan 175d5c3ff3SJiafei Panifneq (${FLASH_TYPE},) 185d5c3ff3SJiafei Pan$(eval $(call add_define,CONFIG_${FLASH_TYPE})) 195d5c3ff3SJiafei Panendif 205d5c3ff3SJiafei Pan 215d5c3ff3SJiafei Panifneq (${XSPI_FLASH_SZ},) 225d5c3ff3SJiafei Pan$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ})) 235d5c3ff3SJiafei Panendif 245d5c3ff3SJiafei Pan 255d5c3ff3SJiafei Panifneq (${QSPI_FLASH_SZ},) 265d5c3ff3SJiafei Pan$(eval $(call add_define_val,NXP_QSPI_FLASH_SIZE,${QSPI_FLASH_SZ})) 275d5c3ff3SJiafei Panendif 285d5c3ff3SJiafei Pan 295d5c3ff3SJiafei Panifneq (${NOR_FLASH_SZ},) 305d5c3ff3SJiafei Pan$(eval $(call add_define_val,NXP_NOR_FLASH_SIZE,${NOR_FLASH_SZ})) 315d5c3ff3SJiafei Panendif 325d5c3ff3SJiafei Pan 335d5c3ff3SJiafei Pan 345d5c3ff3SJiafei Panifneq (${FSPI_ERASE_4K},) 355d5c3ff3SJiafei Pan$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K})) 365d5c3ff3SJiafei Panendif 375d5c3ff3SJiafei Pan 385d5c3ff3SJiafei Panifneq (${NUM_OF_DDRC},) 395d5c3ff3SJiafei Pan$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC})) 405d5c3ff3SJiafei Panendif 415d5c3ff3SJiafei Pan 425d5c3ff3SJiafei Panifeq (${CONFIG_DDR_NODIMM},1) 435d5c3ff3SJiafei Pan$(eval $(call add_define,CONFIG_DDR_NODIMM)) 445d5c3ff3SJiafei PanDDRC_NUM_DIMM := 1 455d5c3ff3SJiafei Panendif 465d5c3ff3SJiafei Pan 475d5c3ff3SJiafei Panifneq (${DDRC_NUM_DIMM},) 485d5c3ff3SJiafei Pan$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM})) 495d5c3ff3SJiafei Panendif 505d5c3ff3SJiafei Pan 515d5c3ff3SJiafei Panifneq (${DDRC_NUM_CS},) 525d5c3ff3SJiafei Pan$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS})) 535d5c3ff3SJiafei Panendif 545d5c3ff3SJiafei Pan 555d5c3ff3SJiafei Panifeq (${DDR_ADDR_DEC},yes) 565d5c3ff3SJiafei Pan$(eval $(call add_define,CONFIG_DDR_ADDR_DEC)) 575d5c3ff3SJiafei Panendif 585d5c3ff3SJiafei Pan 595d5c3ff3SJiafei Panifeq (${DDR_ECC_EN},yes) 605d5c3ff3SJiafei Pan$(eval $(call add_define,CONFIG_DDR_ECC_EN)) 615d5c3ff3SJiafei Panendif 625d5c3ff3SJiafei Pan 635d5c3ff3SJiafei Panifeq (${CONFIG_STATIC_DDR},1) 645d5c3ff3SJiafei Pan$(eval $(call add_define,CONFIG_STATIC_DDR)) 655d5c3ff3SJiafei Panendif 665d5c3ff3SJiafei Pan 675d5c3ff3SJiafei Pan# Platform can control the base address for non-volatile storage. 685d5c3ff3SJiafei Pan#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}')) 695d5c3ff3SJiafei Pan 705d5c3ff3SJiafei Panifeq (${WARM_BOOT},yes) 715d5c3ff3SJiafei Pan$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}')) 725d5c3ff3SJiafei Panendif 73*cd1280eaSJiafei Pan 74*cd1280eaSJiafei Pan# Selecting Boot Source for the TFA images. 75*cd1280eaSJiafei Pandefine add_boot_mode_define 76*cd1280eaSJiafei Pan ifeq ($(1),qspi) 77*cd1280eaSJiafei Pan $$(eval $$(call SET_NXP_MAKE_FLAG,QSPI_NEEDED,BL2)) 78*cd1280eaSJiafei Pan $$(eval $$(call add_define,QSPI_BOOT)) 79*cd1280eaSJiafei Pan else ifeq ($(1),sd) 80*cd1280eaSJiafei Pan $$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2)) 81*cd1280eaSJiafei Pan $$(eval $$(call add_define,SD_BOOT)) 82*cd1280eaSJiafei Pan else ifeq ($(1),emmc) 83*cd1280eaSJiafei Pan $$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2)) 84*cd1280eaSJiafei Pan $$(eval $$(call add_define,EMMC_BOOT)) 85*cd1280eaSJiafei Pan else ifeq ($(1),nor) 86*cd1280eaSJiafei Pan $$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NOR_NEEDED,BL2)) 87*cd1280eaSJiafei Pan $$(eval $$(call add_define,NOR_BOOT)) 88*cd1280eaSJiafei Pan else ifeq ($(1),nand) 89*cd1280eaSJiafei Pan $$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NAND_NEEDED,BL2)) 90*cd1280eaSJiafei Pan $$(eval $$(call add_define,NAND_BOOT)) 91*cd1280eaSJiafei Pan else ifeq ($(1),flexspi_nor) 92*cd1280eaSJiafei Pan $$(eval $$(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2)) 93*cd1280eaSJiafei Pan $$(eval $$(call add_define,FLEXSPI_NOR_BOOT)) 94*cd1280eaSJiafei Pan else 95*cd1280eaSJiafei Pan $$(error $(PLAT) Cannot Support Boot Mode: $(BOOT_MODE)) 96*cd1280eaSJiafei Pan endif 97*cd1280eaSJiafei Panendef 98*cd1280eaSJiafei Pan 99*cd1280eaSJiafei Panifneq (,$(findstring $(BOOT_MODE),$(SUPPORTED_BOOT_MODE))) 100*cd1280eaSJiafei Pan $(eval $(call add_boot_mode_define,$(strip $(BOOT_MODE)))) 101*cd1280eaSJiafei Panelse 102*cd1280eaSJiafei Pan $(error $(PLAT) Un-supported Boot Mode = $(BOOT_MODE)) 103*cd1280eaSJiafei Panendif 104