1# 2# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are met: 6# 7# Redistributions of source code must retain the above copyright notice, this 8# list of conditions and the following disclaimer. 9# 10# Redistributions in binary form must reproduce the above copyright notice, 11# this list of conditions and the following disclaimer in the documentation 12# and/or other materials provided with the distribution. 13# 14# Neither the name of ARM nor the names of its contributors may be used 15# to endorse or promote products derived from this software without specific 16# prior written permission. 17# 18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28# POSSIBILITY OF SUCH DAMAGE. 29# 30 31TEGRA_BOOT_UART_BASE := 0x70006000 32$(eval $(call add_define,TEGRA_BOOT_UART_BASE)) 33 34TZDRAM_BASE := 0xFDC00000 35$(eval $(call add_define,TZDRAM_BASE)) 36 37ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1 38$(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT)) 39 40ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1 41$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS)) 42 43PLATFORM_CLUSTER_COUNT := 2 44$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) 45 46PLATFORM_MAX_CPUS_PER_CLUSTER := 4 47$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) 48 49BL31_SOURCES += ${SOC_DIR}/plat_psci_handlers.c \ 50 ${SOC_DIR}/plat_setup.c \ 51 ${SOC_DIR}/plat_secondary.c 52 53# Enable workarounds for selected Cortex-A53 erratas. 54ERRATA_A53_826319 := 1 55 56