1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <console.h> 32 #include <tegra_def.h> 33 #include <xlat_tables.h> 34 35 /******************************************************************************* 36 * The Tegra power domain tree has a single system level power domain i.e. a 37 * single root node. The first entry in the power domain descriptor specifies 38 * the number of power domains at the highest power level. 39 ******************************************************************************* 40 */ 41 const unsigned char tegra_power_domain_tree_desc[] = { 42 /* No of root nodes */ 43 1, 44 /* No of clusters */ 45 PLATFORM_CLUSTER_COUNT, 46 /* No of CPU cores - cluster0 */ 47 PLATFORM_MAX_CPUS_PER_CLUSTER, 48 /* No of CPU cores - cluster1 */ 49 PLATFORM_MAX_CPUS_PER_CLUSTER 50 }; 51 52 /* sets of MMIO ranges setup */ 53 #define MMIO_RANGE_0_ADDR 0x50000000 54 #define MMIO_RANGE_1_ADDR 0x60000000 55 #define MMIO_RANGE_2_ADDR 0x70000000 56 #define MMIO_RANGE_SIZE 0x200000 57 58 /* 59 * Table of regions to map using the MMU. 60 */ 61 static const mmap_region_t tegra_mmap[] = { 62 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 63 MT_DEVICE | MT_RW | MT_SECURE), 64 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 65 MT_DEVICE | MT_RW | MT_SECURE), 66 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 67 MT_DEVICE | MT_RW | MT_SECURE), 68 {0} 69 }; 70 71 /******************************************************************************* 72 * Set up the pagetables as per the platform memory map & initialize the MMU 73 ******************************************************************************/ 74 const mmap_region_t *plat_get_mmio_map(void) 75 { 76 /* MMIO space */ 77 return tegra_mmap; 78 } 79 80 /******************************************************************************* 81 * Handler to get the System Counter Frequency 82 ******************************************************************************/ 83 unsigned int plat_get_syscnt_freq2(void) 84 { 85 return 19200000; 86 } 87 88 /******************************************************************************* 89 * Maximum supported UART controllers 90 ******************************************************************************/ 91 #define TEGRA210_MAX_UART_PORTS 5 92 93 /******************************************************************************* 94 * This variable holds the UART port base addresses 95 ******************************************************************************/ 96 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 97 0, /* undefined - treated as an error case */ 98 TEGRA_UARTA_BASE, 99 TEGRA_UARTB_BASE, 100 TEGRA_UARTC_BASE, 101 TEGRA_UARTD_BASE, 102 TEGRA_UARTE_BASE, 103 }; 104 105 /******************************************************************************* 106 * Retrieve the UART controller base to be used as the console 107 ******************************************************************************/ 108 uint32_t plat_get_console_from_id(int id) 109 { 110 if (id > TEGRA210_MAX_UART_PORTS) 111 return 0; 112 113 return tegra210_uart_addresses[id]; 114 } 115