1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <bpmp.h> 9 #include <cortex_a57.h> 10 #include <common/bl_common.h> 11 #include <drivers/console.h> 12 #include <lib/xlat_tables/xlat_tables_v2.h> 13 #include <platform.h> 14 #include <security_engine.h> 15 #include <tegra_def.h> 16 #include <tegra_platform.h> 17 #include <tegra_private.h> 18 19 /* sets of MMIO ranges setup */ 20 #define MMIO_RANGE_0_ADDR 0x50000000 21 #define MMIO_RANGE_1_ADDR 0x60000000 22 #define MMIO_RANGE_2_ADDR 0x70000000 23 #define MMIO_RANGE_SIZE 0x200000 24 25 /* 26 * Table of regions to map using the MMU. 27 */ 28 static const mmap_region_t tegra_mmap[] = { 29 MAP_REGION_FLAT(TEGRA_IRAM_BASE, 0x40000, /* 256KB */ 30 MT_DEVICE | MT_RW | MT_SECURE), 31 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 32 MT_DEVICE | MT_RW | MT_SECURE), 33 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 34 MT_DEVICE | MT_RW | MT_SECURE), 35 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 36 MT_DEVICE | MT_RW | MT_SECURE), 37 {0} 38 }; 39 40 /******************************************************************************* 41 * Set up the pagetables as per the platform memory map & initialize the MMU 42 ******************************************************************************/ 43 const mmap_region_t *plat_get_mmio_map(void) 44 { 45 /* Add the map region for security engine SE2 */ 46 if (tegra_chipid_is_t210_b01()) { 47 mmap_add_region((uint64_t)TEGRA_SE2_BASE, 48 (uint64_t)TEGRA_SE2_BASE, 49 (uint64_t)TEGRA_SE2_RANGE_SIZE, 50 MT_DEVICE | MT_RW | MT_SECURE); 51 } 52 53 /* MMIO space */ 54 return tegra_mmap; 55 } 56 57 /******************************************************************************* 58 * The Tegra power domain tree has a single system level power domain i.e. a 59 * single root node. The first entry in the power domain descriptor specifies 60 * the number of power domains at the highest power level. 61 ******************************************************************************* 62 */ 63 const unsigned char tegra_power_domain_tree_desc[] = { 64 /* No of root nodes */ 65 1, 66 /* No of clusters */ 67 PLATFORM_CLUSTER_COUNT, 68 /* No of CPU cores - cluster0 */ 69 PLATFORM_MAX_CPUS_PER_CLUSTER, 70 /* No of CPU cores - cluster1 */ 71 PLATFORM_MAX_CPUS_PER_CLUSTER 72 }; 73 74 /******************************************************************************* 75 * This function returns the Tegra default topology tree information. 76 ******************************************************************************/ 77 const unsigned char *plat_get_power_domain_tree_desc(void) 78 { 79 return tegra_power_domain_tree_desc; 80 } 81 82 /******************************************************************************* 83 * Handler to get the System Counter Frequency 84 ******************************************************************************/ 85 unsigned int plat_get_syscnt_freq2(void) 86 { 87 return 19200000; 88 } 89 90 /******************************************************************************* 91 * Maximum supported UART controllers 92 ******************************************************************************/ 93 #define TEGRA210_MAX_UART_PORTS 5 94 95 /******************************************************************************* 96 * This variable holds the UART port base addresses 97 ******************************************************************************/ 98 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 99 0, /* undefined - treated as an error case */ 100 TEGRA_UARTA_BASE, 101 TEGRA_UARTB_BASE, 102 TEGRA_UARTC_BASE, 103 TEGRA_UARTD_BASE, 104 TEGRA_UARTE_BASE, 105 }; 106 107 /******************************************************************************* 108 * Retrieve the UART controller base to be used as the console 109 ******************************************************************************/ 110 uint32_t plat_get_console_from_id(int id) 111 { 112 if (id > TEGRA210_MAX_UART_PORTS) 113 return 0; 114 115 return tegra210_uart_addresses[id]; 116 } 117 118 /******************************************************************************* 119 * Handler for early platform setup 120 ******************************************************************************/ 121 void plat_early_platform_setup(void) 122 { 123 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 124 uint64_t val; 125 126 /* platform parameter passed by the previous bootloader */ 127 if (plat_params->l2_ecc_parity_prot_dis != 1) { 128 /* Enable ECC Parity Protection for Cortex-A57 CPUs */ 129 val = read_l2ctlr_el1(); 130 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 131 write_l2ctlr_el1(val); 132 } 133 134 /* Initialize security engine driver */ 135 if (tegra_chipid_is_t210_b01()) { 136 tegra_se_init(); 137 } 138 } 139 140 /******************************************************************************* 141 * Initialize the GIC and SGIs 142 ******************************************************************************/ 143 void plat_gic_setup(void) 144 { 145 tegra_gic_setup(NULL, 0); 146 } 147