1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <bpmp.h> 9 #include <common/bl_common.h> 10 #include <drivers/console.h> 11 #include <lib/xlat_tables/xlat_tables_v2.h> 12 #include <platform.h> 13 #include <security_engine.h> 14 #include <tegra_def.h> 15 #include <tegra_platform.h> 16 #include <tegra_private.h> 17 18 /* sets of MMIO ranges setup */ 19 #define MMIO_RANGE_0_ADDR 0x50000000 20 #define MMIO_RANGE_1_ADDR 0x60000000 21 #define MMIO_RANGE_2_ADDR 0x70000000 22 #define MMIO_RANGE_SIZE 0x200000 23 24 /* 25 * Table of regions to map using the MMU. 26 */ 27 static const mmap_region_t tegra_mmap[] = { 28 MAP_REGION_FLAT(TEGRA_IRAM_BASE, 0x40000, /* 256KB */ 29 MT_DEVICE | MT_RW | MT_SECURE), 30 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 31 MT_DEVICE | MT_RW | MT_SECURE), 32 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 33 MT_DEVICE | MT_RW | MT_SECURE), 34 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 35 MT_DEVICE | MT_RW | MT_SECURE), 36 {0} 37 }; 38 39 /******************************************************************************* 40 * Set up the pagetables as per the platform memory map & initialize the MMU 41 ******************************************************************************/ 42 const mmap_region_t *plat_get_mmio_map(void) 43 { 44 /* Add the map region for security engine SE2 */ 45 if (tegra_chipid_is_t210_b01()) { 46 mmap_add_region((uint64_t)TEGRA_SE2_BASE, 47 (uint64_t)TEGRA_SE2_BASE, 48 (uint64_t)TEGRA_SE2_RANGE_SIZE, 49 MT_DEVICE | MT_RW | MT_SECURE); 50 } 51 52 /* MMIO space */ 53 return tegra_mmap; 54 } 55 56 /******************************************************************************* 57 * The Tegra power domain tree has a single system level power domain i.e. a 58 * single root node. The first entry in the power domain descriptor specifies 59 * the number of power domains at the highest power level. 60 ******************************************************************************* 61 */ 62 const unsigned char tegra_power_domain_tree_desc[] = { 63 /* No of root nodes */ 64 1, 65 /* No of clusters */ 66 PLATFORM_CLUSTER_COUNT, 67 /* No of CPU cores - cluster0 */ 68 PLATFORM_MAX_CPUS_PER_CLUSTER, 69 /* No of CPU cores - cluster1 */ 70 PLATFORM_MAX_CPUS_PER_CLUSTER 71 }; 72 73 /******************************************************************************* 74 * This function returns the Tegra default topology tree information. 75 ******************************************************************************/ 76 const unsigned char *plat_get_power_domain_tree_desc(void) 77 { 78 return tegra_power_domain_tree_desc; 79 } 80 81 /******************************************************************************* 82 * Handler to get the System Counter Frequency 83 ******************************************************************************/ 84 unsigned int plat_get_syscnt_freq2(void) 85 { 86 return 19200000; 87 } 88 89 /******************************************************************************* 90 * Maximum supported UART controllers 91 ******************************************************************************/ 92 #define TEGRA210_MAX_UART_PORTS 5 93 94 /******************************************************************************* 95 * This variable holds the UART port base addresses 96 ******************************************************************************/ 97 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 98 0, /* undefined - treated as an error case */ 99 TEGRA_UARTA_BASE, 100 TEGRA_UARTB_BASE, 101 TEGRA_UARTC_BASE, 102 TEGRA_UARTD_BASE, 103 TEGRA_UARTE_BASE, 104 }; 105 106 /******************************************************************************* 107 * Retrieve the UART controller base to be used as the console 108 ******************************************************************************/ 109 uint32_t plat_get_console_from_id(int id) 110 { 111 if (id > TEGRA210_MAX_UART_PORTS) 112 return 0; 113 114 return tegra210_uart_addresses[id]; 115 } 116 117 /******************************************************************************* 118 * Handler for early platform setup 119 ******************************************************************************/ 120 void plat_early_platform_setup(void) 121 { 122 /* Initialize security engine driver */ 123 if (tegra_chipid_is_t210_b01()) { 124 tegra_se_init(); 125 } 126 } 127 128 /******************************************************************************* 129 * Initialize the GIC and SGIs 130 ******************************************************************************/ 131 void plat_gic_setup(void) 132 { 133 tegra_gic_setup(NULL, 0); 134 } 135