1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <bpmp.h> 9 #include <common/bl_common.h> 10 #include <drivers/console.h> 11 #include <lib/xlat_tables/xlat_tables_v2.h> 12 #include <platform.h> 13 #include <security_engine.h> 14 #include <tegra_def.h> 15 #include <tegra_platform.h> 16 #include <tegra_private.h> 17 18 /* sets of MMIO ranges setup */ 19 #define MMIO_RANGE_0_ADDR 0x50000000 20 #define MMIO_RANGE_1_ADDR 0x60000000 21 #define MMIO_RANGE_2_ADDR 0x70000000 22 #define MMIO_RANGE_SIZE 0x200000 23 24 /* 25 * Table of regions to map using the MMU. 26 */ 27 static const mmap_region_t tegra_mmap[] = { 28 MAP_REGION_FLAT(TEGRA_IRAMA_BASE, 0x10000, /* 64KB */ 29 MT_DEVICE | MT_RW | MT_SECURE), 30 MAP_REGION_FLAT(TEGRA_IRAMB_BASE, 0x10000, /* 64KB */ 31 MT_DEVICE | MT_RW | MT_SECURE), 32 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 33 MT_DEVICE | MT_RW | MT_SECURE), 34 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 35 MT_DEVICE | MT_RW | MT_SECURE), 36 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 37 MT_DEVICE | MT_RW | MT_SECURE), 38 {0} 39 }; 40 41 /******************************************************************************* 42 * Set up the pagetables as per the platform memory map & initialize the MMU 43 ******************************************************************************/ 44 const mmap_region_t *plat_get_mmio_map(void) 45 { 46 /* Add the map region for security engine SE2 */ 47 if (tegra_chipid_is_t210_b01()) { 48 mmap_add_region((uint64_t)TEGRA_SE2_BASE, 49 (uint64_t)TEGRA_SE2_BASE, 50 (uint64_t)TEGRA_SE2_RANGE_SIZE, 51 MT_DEVICE | MT_RW | MT_SECURE); 52 } 53 54 /* MMIO space */ 55 return tegra_mmap; 56 } 57 58 /******************************************************************************* 59 * The Tegra power domain tree has a single system level power domain i.e. a 60 * single root node. The first entry in the power domain descriptor specifies 61 * the number of power domains at the highest power level. 62 ******************************************************************************* 63 */ 64 const unsigned char tegra_power_domain_tree_desc[] = { 65 /* No of root nodes */ 66 1, 67 /* No of clusters */ 68 PLATFORM_CLUSTER_COUNT, 69 /* No of CPU cores - cluster0 */ 70 PLATFORM_MAX_CPUS_PER_CLUSTER, 71 /* No of CPU cores - cluster1 */ 72 PLATFORM_MAX_CPUS_PER_CLUSTER 73 }; 74 75 /******************************************************************************* 76 * This function returns the Tegra default topology tree information. 77 ******************************************************************************/ 78 const unsigned char *plat_get_power_domain_tree_desc(void) 79 { 80 return tegra_power_domain_tree_desc; 81 } 82 83 /******************************************************************************* 84 * Handler to get the System Counter Frequency 85 ******************************************************************************/ 86 unsigned int plat_get_syscnt_freq2(void) 87 { 88 return 19200000; 89 } 90 91 /******************************************************************************* 92 * Maximum supported UART controllers 93 ******************************************************************************/ 94 #define TEGRA210_MAX_UART_PORTS 5 95 96 /******************************************************************************* 97 * This variable holds the UART port base addresses 98 ******************************************************************************/ 99 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 100 0, /* undefined - treated as an error case */ 101 TEGRA_UARTA_BASE, 102 TEGRA_UARTB_BASE, 103 TEGRA_UARTC_BASE, 104 TEGRA_UARTD_BASE, 105 TEGRA_UARTE_BASE, 106 }; 107 108 /******************************************************************************* 109 * Retrieve the UART controller base to be used as the console 110 ******************************************************************************/ 111 uint32_t plat_get_console_from_id(int id) 112 { 113 if (id > TEGRA210_MAX_UART_PORTS) 114 return 0; 115 116 return tegra210_uart_addresses[id]; 117 } 118 119 /******************************************************************************* 120 * Handler for early platform setup 121 ******************************************************************************/ 122 void plat_early_platform_setup(void) 123 { 124 /* Initialize security engine driver */ 125 if (tegra_chipid_is_t210_b01()) { 126 tegra_se_init(); 127 } 128 } 129 130 /******************************************************************************* 131 * Initialize the GIC and SGIs 132 ******************************************************************************/ 133 void plat_gic_setup(void) 134 { 135 tegra_gic_setup(NULL, 0); 136 } 137