1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <bl_common.h> 33 #include <console.h> 34 #include <tegra_def.h> 35 #include <tegra_private.h> 36 #include <xlat_tables.h> 37 38 /******************************************************************************* 39 * The Tegra power domain tree has a single system level power domain i.e. a 40 * single root node. The first entry in the power domain descriptor specifies 41 * the number of power domains at the highest power level. 42 ******************************************************************************* 43 */ 44 const unsigned char tegra_power_domain_tree_desc[] = { 45 /* No of root nodes */ 46 1, 47 /* No of clusters */ 48 PLATFORM_CLUSTER_COUNT, 49 /* No of CPU cores - cluster0 */ 50 PLATFORM_MAX_CPUS_PER_CLUSTER, 51 /* No of CPU cores - cluster1 */ 52 PLATFORM_MAX_CPUS_PER_CLUSTER 53 }; 54 55 /* sets of MMIO ranges setup */ 56 #define MMIO_RANGE_0_ADDR 0x50000000 57 #define MMIO_RANGE_1_ADDR 0x60000000 58 #define MMIO_RANGE_2_ADDR 0x70000000 59 #define MMIO_RANGE_SIZE 0x200000 60 61 /* 62 * Table of regions to map using the MMU. 63 */ 64 static const mmap_region_t tegra_mmap[] = { 65 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 66 MT_DEVICE | MT_RW | MT_SECURE), 67 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 68 MT_DEVICE | MT_RW | MT_SECURE), 69 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 70 MT_DEVICE | MT_RW | MT_SECURE), 71 {0} 72 }; 73 74 /******************************************************************************* 75 * Set up the pagetables as per the platform memory map & initialize the MMU 76 ******************************************************************************/ 77 const mmap_region_t *plat_get_mmio_map(void) 78 { 79 /* MMIO space */ 80 return tegra_mmap; 81 } 82 83 /******************************************************************************* 84 * Handler to get the System Counter Frequency 85 ******************************************************************************/ 86 unsigned int plat_get_syscnt_freq2(void) 87 { 88 return 19200000; 89 } 90 91 /******************************************************************************* 92 * Maximum supported UART controllers 93 ******************************************************************************/ 94 #define TEGRA210_MAX_UART_PORTS 5 95 96 /******************************************************************************* 97 * This variable holds the UART port base addresses 98 ******************************************************************************/ 99 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 100 0, /* undefined - treated as an error case */ 101 TEGRA_UARTA_BASE, 102 TEGRA_UARTB_BASE, 103 TEGRA_UARTC_BASE, 104 TEGRA_UARTD_BASE, 105 TEGRA_UARTE_BASE, 106 }; 107 108 /******************************************************************************* 109 * Retrieve the UART controller base to be used as the console 110 ******************************************************************************/ 111 uint32_t plat_get_console_from_id(int id) 112 { 113 if (id > TEGRA210_MAX_UART_PORTS) 114 return 0; 115 116 return tegra210_uart_addresses[id]; 117 } 118 119 /******************************************************************************* 120 * Initialize the GIC and SGIs 121 ******************************************************************************/ 122 void plat_gic_setup(void) 123 { 124 tegra_gic_setup(NULL, 0); 125 } 126