1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <cortex_a57.h> 9 #include <common/bl_common.h> 10 #include <common/debug.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/console.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <drivers/arm/gic_common.h> 15 #include <drivers/arm/gicv2.h> 16 #include <bl31/interrupt_mgmt.h> 17 18 #include <bpmp.h> 19 #include <flowctrl.h> 20 #include <platform.h> 21 #include <security_engine.h> 22 #include <tegra_def.h> 23 #include <tegra_platform.h> 24 #include <tegra_private.h> 25 26 /* sets of MMIO ranges setup */ 27 #define MMIO_RANGE_0_ADDR 0x50000000 28 #define MMIO_RANGE_1_ADDR 0x60000000 29 #define MMIO_RANGE_2_ADDR 0x70000000 30 #define MMIO_RANGE_SIZE 0x200000 31 32 /* 33 * Table of regions to map using the MMU. 34 */ 35 static const mmap_region_t tegra_mmap[] = { 36 MAP_REGION_FLAT(TEGRA_IRAM_BASE, 0x40000, /* 256KB */ 37 MT_DEVICE | MT_RW | MT_SECURE), 38 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 39 MT_DEVICE | MT_RW | MT_SECURE), 40 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 41 MT_DEVICE | MT_RW | MT_SECURE), 42 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 43 MT_DEVICE | MT_RW | MT_SECURE), 44 {0} 45 }; 46 47 /******************************************************************************* 48 * Set up the pagetables as per the platform memory map & initialize the MMU 49 ******************************************************************************/ 50 const mmap_region_t *plat_get_mmio_map(void) 51 { 52 /* Add the map region for security engine SE2 */ 53 if (tegra_chipid_is_t210_b01()) { 54 mmap_add_region((uint64_t)TEGRA_SE2_BASE, 55 (uint64_t)TEGRA_SE2_BASE, 56 (uint64_t)TEGRA_SE2_RANGE_SIZE, 57 MT_DEVICE | MT_RW | MT_SECURE); 58 } 59 60 /* MMIO space */ 61 return tegra_mmap; 62 } 63 64 /******************************************************************************* 65 * The Tegra power domain tree has a single system level power domain i.e. a 66 * single root node. The first entry in the power domain descriptor specifies 67 * the number of power domains at the highest power level. 68 ******************************************************************************* 69 */ 70 const unsigned char tegra_power_domain_tree_desc[] = { 71 /* No of root nodes */ 72 1, 73 /* No of clusters */ 74 PLATFORM_CLUSTER_COUNT, 75 /* No of CPU cores - cluster0 */ 76 PLATFORM_MAX_CPUS_PER_CLUSTER, 77 /* No of CPU cores - cluster1 */ 78 PLATFORM_MAX_CPUS_PER_CLUSTER 79 }; 80 81 /******************************************************************************* 82 * This function returns the Tegra default topology tree information. 83 ******************************************************************************/ 84 const unsigned char *plat_get_power_domain_tree_desc(void) 85 { 86 return tegra_power_domain_tree_desc; 87 } 88 89 /******************************************************************************* 90 * Handler to get the System Counter Frequency 91 ******************************************************************************/ 92 unsigned int plat_get_syscnt_freq2(void) 93 { 94 return 19200000; 95 } 96 97 /******************************************************************************* 98 * Maximum supported UART controllers 99 ******************************************************************************/ 100 #define TEGRA210_MAX_UART_PORTS 5 101 102 /******************************************************************************* 103 * This variable holds the UART port base addresses 104 ******************************************************************************/ 105 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 106 0, /* undefined - treated as an error case */ 107 TEGRA_UARTA_BASE, 108 TEGRA_UARTB_BASE, 109 TEGRA_UARTC_BASE, 110 TEGRA_UARTD_BASE, 111 TEGRA_UARTE_BASE, 112 }; 113 114 /******************************************************************************* 115 * Retrieve the UART controller base to be used as the console 116 ******************************************************************************/ 117 uint32_t plat_get_console_from_id(int id) 118 { 119 if (id > TEGRA210_MAX_UART_PORTS) 120 return 0; 121 122 return tegra210_uart_addresses[id]; 123 } 124 125 /******************************************************************************* 126 * Handler for early platform setup 127 ******************************************************************************/ 128 void plat_early_platform_setup(void) 129 { 130 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 131 uint64_t val; 132 133 /* platform parameter passed by the previous bootloader */ 134 if (plat_params->l2_ecc_parity_prot_dis != 1) { 135 /* Enable ECC Parity Protection for Cortex-A57 CPUs */ 136 val = read_l2ctlr_el1(); 137 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 138 write_l2ctlr_el1(val); 139 } 140 141 /* Initialize security engine driver */ 142 if (tegra_chipid_is_t210_b01()) { 143 tegra_se_init(); 144 } 145 } 146 147 /* Secure IRQs for Tegra186 */ 148 static const interrupt_prop_t tegra210_interrupt_props[] = { 149 INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, GIC_HIGHEST_SEC_PRIORITY, 150 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 151 }; 152 153 /******************************************************************************* 154 * Initialize the GIC and SGIs 155 ******************************************************************************/ 156 void plat_gic_setup(void) 157 { 158 tegra_gic_setup(tegra210_interrupt_props, ARRAY_SIZE(tegra210_interrupt_props)); 159 160 /* Enable handling for FIQs */ 161 tegra_fiq_handler_setup(); 162 163 /* 164 * Enable routing watchdog FIQs from the flow controller to 165 * the GICD. 166 */ 167 tegra_fc_enable_fiq_to_ccplex_routing(); 168 } 169