108438e24SVarun Wadekar /* 208438e24SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 408438e24SVarun Wadekar * Redistribution and use in source and binary forms, with or without 508438e24SVarun Wadekar * modification, are permitted provided that the following conditions are met: 608438e24SVarun Wadekar * 708438e24SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 808438e24SVarun Wadekar * list of conditions and the following disclaimer. 908438e24SVarun Wadekar * 1008438e24SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 1108438e24SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 1208438e24SVarun Wadekar * and/or other materials provided with the distribution. 1308438e24SVarun Wadekar * 1408438e24SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 1508438e24SVarun Wadekar * to endorse or promote products derived from this software without specific 1608438e24SVarun Wadekar * prior written permission. 1708438e24SVarun Wadekar * 1808438e24SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1908438e24SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2008438e24SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2108438e24SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2208438e24SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2308438e24SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2408438e24SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2508438e24SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2608438e24SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2708438e24SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2808438e24SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 2908438e24SVarun Wadekar */ 3008438e24SVarun Wadekar 3108438e24SVarun Wadekar #include <console.h> 3208438e24SVarun Wadekar #include <tegra_def.h> 3308438e24SVarun Wadekar #include <xlat_tables.h> 3408438e24SVarun Wadekar 3571cb26eaSVarun Wadekar /******************************************************************************* 3671cb26eaSVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 3771cb26eaSVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 3871cb26eaSVarun Wadekar * the number of power domains at the highest power level. 3971cb26eaSVarun Wadekar ******************************************************************************* 4071cb26eaSVarun Wadekar */ 4171cb26eaSVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 4271cb26eaSVarun Wadekar /* No of root nodes */ 4371cb26eaSVarun Wadekar 1, 4471cb26eaSVarun Wadekar /* No of clusters */ 4571cb26eaSVarun Wadekar PLATFORM_CLUSTER_COUNT, 4671cb26eaSVarun Wadekar /* No of CPU cores - cluster0 */ 4771cb26eaSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 4871cb26eaSVarun Wadekar /* No of CPU cores - cluster1 */ 4971cb26eaSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 5071cb26eaSVarun Wadekar }; 5171cb26eaSVarun Wadekar 5208438e24SVarun Wadekar /* sets of MMIO ranges setup */ 5308438e24SVarun Wadekar #define MMIO_RANGE_0_ADDR 0x50000000 5408438e24SVarun Wadekar #define MMIO_RANGE_1_ADDR 0x60000000 5508438e24SVarun Wadekar #define MMIO_RANGE_2_ADDR 0x70000000 5608438e24SVarun Wadekar #define MMIO_RANGE_SIZE 0x200000 5708438e24SVarun Wadekar 5808438e24SVarun Wadekar /* 5908438e24SVarun Wadekar * Table of regions to map using the MMU. 6008438e24SVarun Wadekar */ 6108438e24SVarun Wadekar static const mmap_region_t tegra_mmap[] = { 6208438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 6308438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 6408438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 6508438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 6608438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 6708438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 6808438e24SVarun Wadekar {0} 6908438e24SVarun Wadekar }; 7008438e24SVarun Wadekar 7108438e24SVarun Wadekar /******************************************************************************* 7208438e24SVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 7308438e24SVarun Wadekar ******************************************************************************/ 7408438e24SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 7508438e24SVarun Wadekar { 7608438e24SVarun Wadekar /* MMIO space */ 7708438e24SVarun Wadekar return tegra_mmap; 7808438e24SVarun Wadekar } 7908438e24SVarun Wadekar 8008438e24SVarun Wadekar /******************************************************************************* 8108438e24SVarun Wadekar * Handler to get the System Counter Frequency 8208438e24SVarun Wadekar ******************************************************************************/ 83f3d3b316SAntonio Nino Diaz unsigned int plat_get_syscnt_freq2(void) 8408438e24SVarun Wadekar { 8508438e24SVarun Wadekar return 19200000; 8608438e24SVarun Wadekar } 87*e1084216SVarun Wadekar 88*e1084216SVarun Wadekar /******************************************************************************* 89*e1084216SVarun Wadekar * Maximum supported UART controllers 90*e1084216SVarun Wadekar ******************************************************************************/ 91*e1084216SVarun Wadekar #define TEGRA210_MAX_UART_PORTS 5 92*e1084216SVarun Wadekar 93*e1084216SVarun Wadekar /******************************************************************************* 94*e1084216SVarun Wadekar * This variable holds the UART port base addresses 95*e1084216SVarun Wadekar ******************************************************************************/ 96*e1084216SVarun Wadekar static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 97*e1084216SVarun Wadekar 0, /* undefined - treated as an error case */ 98*e1084216SVarun Wadekar TEGRA_UARTA_BASE, 99*e1084216SVarun Wadekar TEGRA_UARTB_BASE, 100*e1084216SVarun Wadekar TEGRA_UARTC_BASE, 101*e1084216SVarun Wadekar TEGRA_UARTD_BASE, 102*e1084216SVarun Wadekar TEGRA_UARTE_BASE, 103*e1084216SVarun Wadekar }; 104*e1084216SVarun Wadekar 105*e1084216SVarun Wadekar /******************************************************************************* 106*e1084216SVarun Wadekar * Retrieve the UART controller base to be used as the console 107*e1084216SVarun Wadekar ******************************************************************************/ 108*e1084216SVarun Wadekar uint32_t plat_get_console_from_id(int id) 109*e1084216SVarun Wadekar { 110*e1084216SVarun Wadekar if (id > TEGRA210_MAX_UART_PORTS) 111*e1084216SVarun Wadekar return 0; 112*e1084216SVarun Wadekar 113*e1084216SVarun Wadekar return tegra210_uart_addresses[id]; 114*e1084216SVarun Wadekar } 115