108438e24SVarun Wadekar /* 2d3360301SVarun Wadekar * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7d3360301SVarun Wadekar #include <arch_helpers.h> 8d3360301SVarun Wadekar #include <bl_common.h> 908438e24SVarun Wadekar #include <console.h> 1008438e24SVarun Wadekar #include <tegra_def.h> 11d3360301SVarun Wadekar #include <tegra_private.h> 1208438e24SVarun Wadekar #include <xlat_tables.h> 1308438e24SVarun Wadekar 1471cb26eaSVarun Wadekar /******************************************************************************* 1571cb26eaSVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 1671cb26eaSVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 1771cb26eaSVarun Wadekar * the number of power domains at the highest power level. 1871cb26eaSVarun Wadekar ******************************************************************************* 1971cb26eaSVarun Wadekar */ 2071cb26eaSVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 2171cb26eaSVarun Wadekar /* No of root nodes */ 2271cb26eaSVarun Wadekar 1, 2371cb26eaSVarun Wadekar /* No of clusters */ 2471cb26eaSVarun Wadekar PLATFORM_CLUSTER_COUNT, 2571cb26eaSVarun Wadekar /* No of CPU cores - cluster0 */ 2671cb26eaSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 2771cb26eaSVarun Wadekar /* No of CPU cores - cluster1 */ 2871cb26eaSVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 2971cb26eaSVarun Wadekar }; 3071cb26eaSVarun Wadekar 3108438e24SVarun Wadekar /* sets of MMIO ranges setup */ 3208438e24SVarun Wadekar #define MMIO_RANGE_0_ADDR 0x50000000 3308438e24SVarun Wadekar #define MMIO_RANGE_1_ADDR 0x60000000 3408438e24SVarun Wadekar #define MMIO_RANGE_2_ADDR 0x70000000 3508438e24SVarun Wadekar #define MMIO_RANGE_SIZE 0x200000 3608438e24SVarun Wadekar 3708438e24SVarun Wadekar /* 3808438e24SVarun Wadekar * Table of regions to map using the MMU. 3908438e24SVarun Wadekar */ 4008438e24SVarun Wadekar static const mmap_region_t tegra_mmap[] = { 4108438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 4208438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 4308438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 4408438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 4508438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 4608438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 4708438e24SVarun Wadekar {0} 4808438e24SVarun Wadekar }; 4908438e24SVarun Wadekar 5008438e24SVarun Wadekar /******************************************************************************* 5108438e24SVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 5208438e24SVarun Wadekar ******************************************************************************/ 5308438e24SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 5408438e24SVarun Wadekar { 5508438e24SVarun Wadekar /* MMIO space */ 5608438e24SVarun Wadekar return tegra_mmap; 5708438e24SVarun Wadekar } 5808438e24SVarun Wadekar 5908438e24SVarun Wadekar /******************************************************************************* 6008438e24SVarun Wadekar * Handler to get the System Counter Frequency 6108438e24SVarun Wadekar ******************************************************************************/ 62f3d3b316SAntonio Nino Diaz unsigned int plat_get_syscnt_freq2(void) 6308438e24SVarun Wadekar { 6408438e24SVarun Wadekar return 19200000; 6508438e24SVarun Wadekar } 66e1084216SVarun Wadekar 67e1084216SVarun Wadekar /******************************************************************************* 68e1084216SVarun Wadekar * Maximum supported UART controllers 69e1084216SVarun Wadekar ******************************************************************************/ 70e1084216SVarun Wadekar #define TEGRA210_MAX_UART_PORTS 5 71e1084216SVarun Wadekar 72e1084216SVarun Wadekar /******************************************************************************* 73e1084216SVarun Wadekar * This variable holds the UART port base addresses 74e1084216SVarun Wadekar ******************************************************************************/ 75e1084216SVarun Wadekar static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 76e1084216SVarun Wadekar 0, /* undefined - treated as an error case */ 77e1084216SVarun Wadekar TEGRA_UARTA_BASE, 78e1084216SVarun Wadekar TEGRA_UARTB_BASE, 79e1084216SVarun Wadekar TEGRA_UARTC_BASE, 80e1084216SVarun Wadekar TEGRA_UARTD_BASE, 81e1084216SVarun Wadekar TEGRA_UARTE_BASE, 82e1084216SVarun Wadekar }; 83e1084216SVarun Wadekar 84e1084216SVarun Wadekar /******************************************************************************* 85e1084216SVarun Wadekar * Retrieve the UART controller base to be used as the console 86e1084216SVarun Wadekar ******************************************************************************/ 87e1084216SVarun Wadekar uint32_t plat_get_console_from_id(int id) 88e1084216SVarun Wadekar { 89e1084216SVarun Wadekar if (id > TEGRA210_MAX_UART_PORTS) 90e1084216SVarun Wadekar return 0; 91e1084216SVarun Wadekar 92e1084216SVarun Wadekar return tegra210_uart_addresses[id]; 93e1084216SVarun Wadekar } 94d3360301SVarun Wadekar 95d3360301SVarun Wadekar /******************************************************************************* 96d3360301SVarun Wadekar * Initialize the GIC and SGIs 97d3360301SVarun Wadekar ******************************************************************************/ 98d3360301SVarun Wadekar void plat_gic_setup(void) 99d3360301SVarun Wadekar { 100d3360301SVarun Wadekar tegra_gic_setup(NULL, 0); 101d3360301SVarun Wadekar } 102