108438e24SVarun Wadekar /* 2*7b3b41d6SVarun Wadekar * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7d3360301SVarun Wadekar #include <arch_helpers.h> 809d40e0eSAntonio Nino Diaz #include <common/bl_common.h> 909d40e0eSAntonio Nino Diaz #include <drivers/console.h> 1009d40e0eSAntonio Nino Diaz #include <lib/xlat_tables/xlat_tables_v2.h> 11*7b3b41d6SVarun Wadekar #include <platform.h> 1208438e24SVarun Wadekar #include <tegra_def.h> 13d3360301SVarun Wadekar #include <tegra_private.h> 1408438e24SVarun Wadekar 1508438e24SVarun Wadekar /* sets of MMIO ranges setup */ 1608438e24SVarun Wadekar #define MMIO_RANGE_0_ADDR 0x50000000 1708438e24SVarun Wadekar #define MMIO_RANGE_1_ADDR 0x60000000 1808438e24SVarun Wadekar #define MMIO_RANGE_2_ADDR 0x70000000 1908438e24SVarun Wadekar #define MMIO_RANGE_SIZE 0x200000 2008438e24SVarun Wadekar 2108438e24SVarun Wadekar /* 2208438e24SVarun Wadekar * Table of regions to map using the MMU. 2308438e24SVarun Wadekar */ 2408438e24SVarun Wadekar static const mmap_region_t tegra_mmap[] = { 2508438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 2608438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 2708438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 2808438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 2908438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 3008438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 3108438e24SVarun Wadekar {0} 3208438e24SVarun Wadekar }; 3308438e24SVarun Wadekar 3408438e24SVarun Wadekar /******************************************************************************* 3508438e24SVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 3608438e24SVarun Wadekar ******************************************************************************/ 3708438e24SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 3808438e24SVarun Wadekar { 3908438e24SVarun Wadekar /* MMIO space */ 4008438e24SVarun Wadekar return tegra_mmap; 4108438e24SVarun Wadekar } 4208438e24SVarun Wadekar 4308438e24SVarun Wadekar /******************************************************************************* 44*7b3b41d6SVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 45*7b3b41d6SVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 46*7b3b41d6SVarun Wadekar * the number of power domains at the highest power level. 47*7b3b41d6SVarun Wadekar ******************************************************************************* 48*7b3b41d6SVarun Wadekar */ 49*7b3b41d6SVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 50*7b3b41d6SVarun Wadekar /* No of root nodes */ 51*7b3b41d6SVarun Wadekar 1, 52*7b3b41d6SVarun Wadekar /* No of clusters */ 53*7b3b41d6SVarun Wadekar PLATFORM_CLUSTER_COUNT, 54*7b3b41d6SVarun Wadekar /* No of CPU cores - cluster0 */ 55*7b3b41d6SVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 56*7b3b41d6SVarun Wadekar /* No of CPU cores - cluster1 */ 57*7b3b41d6SVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 58*7b3b41d6SVarun Wadekar }; 59*7b3b41d6SVarun Wadekar 60*7b3b41d6SVarun Wadekar /******************************************************************************* 61*7b3b41d6SVarun Wadekar * This function returns the Tegra default topology tree information. 62*7b3b41d6SVarun Wadekar ******************************************************************************/ 63*7b3b41d6SVarun Wadekar const unsigned char *plat_get_power_domain_tree_desc(void) 64*7b3b41d6SVarun Wadekar { 65*7b3b41d6SVarun Wadekar return tegra_power_domain_tree_desc; 66*7b3b41d6SVarun Wadekar } 67*7b3b41d6SVarun Wadekar 68*7b3b41d6SVarun Wadekar /******************************************************************************* 6908438e24SVarun Wadekar * Handler to get the System Counter Frequency 7008438e24SVarun Wadekar ******************************************************************************/ 71f3d3b316SAntonio Nino Diaz unsigned int plat_get_syscnt_freq2(void) 7208438e24SVarun Wadekar { 7308438e24SVarun Wadekar return 19200000; 7408438e24SVarun Wadekar } 75e1084216SVarun Wadekar 76e1084216SVarun Wadekar /******************************************************************************* 77e1084216SVarun Wadekar * Maximum supported UART controllers 78e1084216SVarun Wadekar ******************************************************************************/ 79e1084216SVarun Wadekar #define TEGRA210_MAX_UART_PORTS 5 80e1084216SVarun Wadekar 81e1084216SVarun Wadekar /******************************************************************************* 82e1084216SVarun Wadekar * This variable holds the UART port base addresses 83e1084216SVarun Wadekar ******************************************************************************/ 84e1084216SVarun Wadekar static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 85e1084216SVarun Wadekar 0, /* undefined - treated as an error case */ 86e1084216SVarun Wadekar TEGRA_UARTA_BASE, 87e1084216SVarun Wadekar TEGRA_UARTB_BASE, 88e1084216SVarun Wadekar TEGRA_UARTC_BASE, 89e1084216SVarun Wadekar TEGRA_UARTD_BASE, 90e1084216SVarun Wadekar TEGRA_UARTE_BASE, 91e1084216SVarun Wadekar }; 92e1084216SVarun Wadekar 93e1084216SVarun Wadekar /******************************************************************************* 94e1084216SVarun Wadekar * Retrieve the UART controller base to be used as the console 95e1084216SVarun Wadekar ******************************************************************************/ 96e1084216SVarun Wadekar uint32_t plat_get_console_from_id(int id) 97e1084216SVarun Wadekar { 98e1084216SVarun Wadekar if (id > TEGRA210_MAX_UART_PORTS) 99e1084216SVarun Wadekar return 0; 100e1084216SVarun Wadekar 101e1084216SVarun Wadekar return tegra210_uart_addresses[id]; 102e1084216SVarun Wadekar } 103d3360301SVarun Wadekar 104d3360301SVarun Wadekar /******************************************************************************* 105d3360301SVarun Wadekar * Initialize the GIC and SGIs 106d3360301SVarun Wadekar ******************************************************************************/ 107d3360301SVarun Wadekar void plat_gic_setup(void) 108d3360301SVarun Wadekar { 109d3360301SVarun Wadekar tegra_gic_setup(NULL, 0); 110d3360301SVarun Wadekar } 111