108438e24SVarun Wadekar /* 27b3b41d6SVarun Wadekar * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7d3360301SVarun Wadekar #include <arch_helpers.h> 8dd1a71f1SVarun Wadekar #include <bpmp.h> 9*53ea1585SSam Payne #include <cortex_a57.h> 1009d40e0eSAntonio Nino Diaz #include <common/bl_common.h> 1109d40e0eSAntonio Nino Diaz #include <drivers/console.h> 1209d40e0eSAntonio Nino Diaz #include <lib/xlat_tables/xlat_tables_v2.h> 137b3b41d6SVarun Wadekar #include <platform.h> 14ce3c97c9SMarvin Hsu #include <security_engine.h> 1508438e24SVarun Wadekar #include <tegra_def.h> 16ce3c97c9SMarvin Hsu #include <tegra_platform.h> 17d3360301SVarun Wadekar #include <tegra_private.h> 1808438e24SVarun Wadekar 1908438e24SVarun Wadekar /* sets of MMIO ranges setup */ 2008438e24SVarun Wadekar #define MMIO_RANGE_0_ADDR 0x50000000 2108438e24SVarun Wadekar #define MMIO_RANGE_1_ADDR 0x60000000 2208438e24SVarun Wadekar #define MMIO_RANGE_2_ADDR 0x70000000 2308438e24SVarun Wadekar #define MMIO_RANGE_SIZE 0x200000 2408438e24SVarun Wadekar 2508438e24SVarun Wadekar /* 2608438e24SVarun Wadekar * Table of regions to map using the MMU. 2708438e24SVarun Wadekar */ 2808438e24SVarun Wadekar static const mmap_region_t tegra_mmap[] = { 29223844afSVarun Wadekar MAP_REGION_FLAT(TEGRA_IRAM_BASE, 0x40000, /* 256KB */ 30dd1a71f1SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 3108438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 3208438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 3308438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 3408438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 3508438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 3608438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 3708438e24SVarun Wadekar {0} 3808438e24SVarun Wadekar }; 3908438e24SVarun Wadekar 4008438e24SVarun Wadekar /******************************************************************************* 4108438e24SVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 4208438e24SVarun Wadekar ******************************************************************************/ 4308438e24SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 4408438e24SVarun Wadekar { 45ce3c97c9SMarvin Hsu /* Add the map region for security engine SE2 */ 46ce3c97c9SMarvin Hsu if (tegra_chipid_is_t210_b01()) { 47ce3c97c9SMarvin Hsu mmap_add_region((uint64_t)TEGRA_SE2_BASE, 48ce3c97c9SMarvin Hsu (uint64_t)TEGRA_SE2_BASE, 49ce3c97c9SMarvin Hsu (uint64_t)TEGRA_SE2_RANGE_SIZE, 50ce3c97c9SMarvin Hsu MT_DEVICE | MT_RW | MT_SECURE); 51ce3c97c9SMarvin Hsu } 52ce3c97c9SMarvin Hsu 5308438e24SVarun Wadekar /* MMIO space */ 5408438e24SVarun Wadekar return tegra_mmap; 5508438e24SVarun Wadekar } 5608438e24SVarun Wadekar 5708438e24SVarun Wadekar /******************************************************************************* 587b3b41d6SVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 597b3b41d6SVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 607b3b41d6SVarun Wadekar * the number of power domains at the highest power level. 617b3b41d6SVarun Wadekar ******************************************************************************* 627b3b41d6SVarun Wadekar */ 637b3b41d6SVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 647b3b41d6SVarun Wadekar /* No of root nodes */ 657b3b41d6SVarun Wadekar 1, 667b3b41d6SVarun Wadekar /* No of clusters */ 677b3b41d6SVarun Wadekar PLATFORM_CLUSTER_COUNT, 687b3b41d6SVarun Wadekar /* No of CPU cores - cluster0 */ 697b3b41d6SVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 707b3b41d6SVarun Wadekar /* No of CPU cores - cluster1 */ 717b3b41d6SVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 727b3b41d6SVarun Wadekar }; 737b3b41d6SVarun Wadekar 747b3b41d6SVarun Wadekar /******************************************************************************* 757b3b41d6SVarun Wadekar * This function returns the Tegra default topology tree information. 767b3b41d6SVarun Wadekar ******************************************************************************/ 777b3b41d6SVarun Wadekar const unsigned char *plat_get_power_domain_tree_desc(void) 787b3b41d6SVarun Wadekar { 797b3b41d6SVarun Wadekar return tegra_power_domain_tree_desc; 807b3b41d6SVarun Wadekar } 817b3b41d6SVarun Wadekar 827b3b41d6SVarun Wadekar /******************************************************************************* 8308438e24SVarun Wadekar * Handler to get the System Counter Frequency 8408438e24SVarun Wadekar ******************************************************************************/ 85f3d3b316SAntonio Nino Diaz unsigned int plat_get_syscnt_freq2(void) 8608438e24SVarun Wadekar { 8708438e24SVarun Wadekar return 19200000; 8808438e24SVarun Wadekar } 89e1084216SVarun Wadekar 90e1084216SVarun Wadekar /******************************************************************************* 91e1084216SVarun Wadekar * Maximum supported UART controllers 92e1084216SVarun Wadekar ******************************************************************************/ 93e1084216SVarun Wadekar #define TEGRA210_MAX_UART_PORTS 5 94e1084216SVarun Wadekar 95e1084216SVarun Wadekar /******************************************************************************* 96e1084216SVarun Wadekar * This variable holds the UART port base addresses 97e1084216SVarun Wadekar ******************************************************************************/ 98e1084216SVarun Wadekar static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 99e1084216SVarun Wadekar 0, /* undefined - treated as an error case */ 100e1084216SVarun Wadekar TEGRA_UARTA_BASE, 101e1084216SVarun Wadekar TEGRA_UARTB_BASE, 102e1084216SVarun Wadekar TEGRA_UARTC_BASE, 103e1084216SVarun Wadekar TEGRA_UARTD_BASE, 104e1084216SVarun Wadekar TEGRA_UARTE_BASE, 105e1084216SVarun Wadekar }; 106e1084216SVarun Wadekar 107e1084216SVarun Wadekar /******************************************************************************* 108e1084216SVarun Wadekar * Retrieve the UART controller base to be used as the console 109e1084216SVarun Wadekar ******************************************************************************/ 110e1084216SVarun Wadekar uint32_t plat_get_console_from_id(int id) 111e1084216SVarun Wadekar { 112e1084216SVarun Wadekar if (id > TEGRA210_MAX_UART_PORTS) 113e1084216SVarun Wadekar return 0; 114e1084216SVarun Wadekar 115e1084216SVarun Wadekar return tegra210_uart_addresses[id]; 116e1084216SVarun Wadekar } 117d3360301SVarun Wadekar 118d3360301SVarun Wadekar /******************************************************************************* 119ce3c97c9SMarvin Hsu * Handler for early platform setup 120ce3c97c9SMarvin Hsu ******************************************************************************/ 121ce3c97c9SMarvin Hsu void plat_early_platform_setup(void) 122ce3c97c9SMarvin Hsu { 123*53ea1585SSam Payne const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 124*53ea1585SSam Payne uint64_t val; 125*53ea1585SSam Payne 126*53ea1585SSam Payne /* platform parameter passed by the previous bootloader */ 127*53ea1585SSam Payne if (plat_params->l2_ecc_parity_prot_dis != 1) { 128*53ea1585SSam Payne /* Enable ECC Parity Protection for Cortex-A57 CPUs */ 129*53ea1585SSam Payne val = read_l2ctlr_el1(); 130*53ea1585SSam Payne val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 131*53ea1585SSam Payne write_l2ctlr_el1(val); 132*53ea1585SSam Payne } 133*53ea1585SSam Payne 134ce3c97c9SMarvin Hsu /* Initialize security engine driver */ 135ce3c97c9SMarvin Hsu if (tegra_chipid_is_t210_b01()) { 136ce3c97c9SMarvin Hsu tegra_se_init(); 137ce3c97c9SMarvin Hsu } 138ce3c97c9SMarvin Hsu } 139ce3c97c9SMarvin Hsu 140ce3c97c9SMarvin Hsu /******************************************************************************* 141d3360301SVarun Wadekar * Initialize the GIC and SGIs 142d3360301SVarun Wadekar ******************************************************************************/ 143d3360301SVarun Wadekar void plat_gic_setup(void) 144d3360301SVarun Wadekar { 145d3360301SVarun Wadekar tegra_gic_setup(NULL, 0); 146d3360301SVarun Wadekar } 147