108438e24SVarun Wadekar /* 27b3b41d6SVarun Wadekar * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 308438e24SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 508438e24SVarun Wadekar */ 608438e24SVarun Wadekar 7d3360301SVarun Wadekar #include <arch_helpers.h> 8dd1a71f1SVarun Wadekar #include <bpmp.h> 909d40e0eSAntonio Nino Diaz #include <common/bl_common.h> 1009d40e0eSAntonio Nino Diaz #include <drivers/console.h> 1109d40e0eSAntonio Nino Diaz #include <lib/xlat_tables/xlat_tables_v2.h> 127b3b41d6SVarun Wadekar #include <platform.h> 13ce3c97c9SMarvin Hsu #include <security_engine.h> 1408438e24SVarun Wadekar #include <tegra_def.h> 15ce3c97c9SMarvin Hsu #include <tegra_platform.h> 16d3360301SVarun Wadekar #include <tegra_private.h> 1708438e24SVarun Wadekar 1808438e24SVarun Wadekar /* sets of MMIO ranges setup */ 1908438e24SVarun Wadekar #define MMIO_RANGE_0_ADDR 0x50000000 2008438e24SVarun Wadekar #define MMIO_RANGE_1_ADDR 0x60000000 2108438e24SVarun Wadekar #define MMIO_RANGE_2_ADDR 0x70000000 2208438e24SVarun Wadekar #define MMIO_RANGE_SIZE 0x200000 2308438e24SVarun Wadekar 2408438e24SVarun Wadekar /* 2508438e24SVarun Wadekar * Table of regions to map using the MMU. 2608438e24SVarun Wadekar */ 2708438e24SVarun Wadekar static const mmap_region_t tegra_mmap[] = { 28*223844afSVarun Wadekar MAP_REGION_FLAT(TEGRA_IRAM_BASE, 0x40000, /* 256KB */ 29dd1a71f1SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 3008438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 3108438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 3208438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 3308438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 3408438e24SVarun Wadekar MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 3508438e24SVarun Wadekar MT_DEVICE | MT_RW | MT_SECURE), 3608438e24SVarun Wadekar {0} 3708438e24SVarun Wadekar }; 3808438e24SVarun Wadekar 3908438e24SVarun Wadekar /******************************************************************************* 4008438e24SVarun Wadekar * Set up the pagetables as per the platform memory map & initialize the MMU 4108438e24SVarun Wadekar ******************************************************************************/ 4208438e24SVarun Wadekar const mmap_region_t *plat_get_mmio_map(void) 4308438e24SVarun Wadekar { 44ce3c97c9SMarvin Hsu /* Add the map region for security engine SE2 */ 45ce3c97c9SMarvin Hsu if (tegra_chipid_is_t210_b01()) { 46ce3c97c9SMarvin Hsu mmap_add_region((uint64_t)TEGRA_SE2_BASE, 47ce3c97c9SMarvin Hsu (uint64_t)TEGRA_SE2_BASE, 48ce3c97c9SMarvin Hsu (uint64_t)TEGRA_SE2_RANGE_SIZE, 49ce3c97c9SMarvin Hsu MT_DEVICE | MT_RW | MT_SECURE); 50ce3c97c9SMarvin Hsu } 51ce3c97c9SMarvin Hsu 5208438e24SVarun Wadekar /* MMIO space */ 5308438e24SVarun Wadekar return tegra_mmap; 5408438e24SVarun Wadekar } 5508438e24SVarun Wadekar 5608438e24SVarun Wadekar /******************************************************************************* 577b3b41d6SVarun Wadekar * The Tegra power domain tree has a single system level power domain i.e. a 587b3b41d6SVarun Wadekar * single root node. The first entry in the power domain descriptor specifies 597b3b41d6SVarun Wadekar * the number of power domains at the highest power level. 607b3b41d6SVarun Wadekar ******************************************************************************* 617b3b41d6SVarun Wadekar */ 627b3b41d6SVarun Wadekar const unsigned char tegra_power_domain_tree_desc[] = { 637b3b41d6SVarun Wadekar /* No of root nodes */ 647b3b41d6SVarun Wadekar 1, 657b3b41d6SVarun Wadekar /* No of clusters */ 667b3b41d6SVarun Wadekar PLATFORM_CLUSTER_COUNT, 677b3b41d6SVarun Wadekar /* No of CPU cores - cluster0 */ 687b3b41d6SVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER, 697b3b41d6SVarun Wadekar /* No of CPU cores - cluster1 */ 707b3b41d6SVarun Wadekar PLATFORM_MAX_CPUS_PER_CLUSTER 717b3b41d6SVarun Wadekar }; 727b3b41d6SVarun Wadekar 737b3b41d6SVarun Wadekar /******************************************************************************* 747b3b41d6SVarun Wadekar * This function returns the Tegra default topology tree information. 757b3b41d6SVarun Wadekar ******************************************************************************/ 767b3b41d6SVarun Wadekar const unsigned char *plat_get_power_domain_tree_desc(void) 777b3b41d6SVarun Wadekar { 787b3b41d6SVarun Wadekar return tegra_power_domain_tree_desc; 797b3b41d6SVarun Wadekar } 807b3b41d6SVarun Wadekar 817b3b41d6SVarun Wadekar /******************************************************************************* 8208438e24SVarun Wadekar * Handler to get the System Counter Frequency 8308438e24SVarun Wadekar ******************************************************************************/ 84f3d3b316SAntonio Nino Diaz unsigned int plat_get_syscnt_freq2(void) 8508438e24SVarun Wadekar { 8608438e24SVarun Wadekar return 19200000; 8708438e24SVarun Wadekar } 88e1084216SVarun Wadekar 89e1084216SVarun Wadekar /******************************************************************************* 90e1084216SVarun Wadekar * Maximum supported UART controllers 91e1084216SVarun Wadekar ******************************************************************************/ 92e1084216SVarun Wadekar #define TEGRA210_MAX_UART_PORTS 5 93e1084216SVarun Wadekar 94e1084216SVarun Wadekar /******************************************************************************* 95e1084216SVarun Wadekar * This variable holds the UART port base addresses 96e1084216SVarun Wadekar ******************************************************************************/ 97e1084216SVarun Wadekar static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 98e1084216SVarun Wadekar 0, /* undefined - treated as an error case */ 99e1084216SVarun Wadekar TEGRA_UARTA_BASE, 100e1084216SVarun Wadekar TEGRA_UARTB_BASE, 101e1084216SVarun Wadekar TEGRA_UARTC_BASE, 102e1084216SVarun Wadekar TEGRA_UARTD_BASE, 103e1084216SVarun Wadekar TEGRA_UARTE_BASE, 104e1084216SVarun Wadekar }; 105e1084216SVarun Wadekar 106e1084216SVarun Wadekar /******************************************************************************* 107e1084216SVarun Wadekar * Retrieve the UART controller base to be used as the console 108e1084216SVarun Wadekar ******************************************************************************/ 109e1084216SVarun Wadekar uint32_t plat_get_console_from_id(int id) 110e1084216SVarun Wadekar { 111e1084216SVarun Wadekar if (id > TEGRA210_MAX_UART_PORTS) 112e1084216SVarun Wadekar return 0; 113e1084216SVarun Wadekar 114e1084216SVarun Wadekar return tegra210_uart_addresses[id]; 115e1084216SVarun Wadekar } 116d3360301SVarun Wadekar 117d3360301SVarun Wadekar /******************************************************************************* 118ce3c97c9SMarvin Hsu * Handler for early platform setup 119ce3c97c9SMarvin Hsu ******************************************************************************/ 120ce3c97c9SMarvin Hsu void plat_early_platform_setup(void) 121ce3c97c9SMarvin Hsu { 122ce3c97c9SMarvin Hsu /* Initialize security engine driver */ 123ce3c97c9SMarvin Hsu if (tegra_chipid_is_t210_b01()) { 124ce3c97c9SMarvin Hsu tegra_se_init(); 125ce3c97c9SMarvin Hsu } 126ce3c97c9SMarvin Hsu } 127ce3c97c9SMarvin Hsu 128ce3c97c9SMarvin Hsu /******************************************************************************* 129d3360301SVarun Wadekar * Initialize the GIC and SGIs 130d3360301SVarun Wadekar ******************************************************************************/ 131d3360301SVarun Wadekar void plat_gic_setup(void) 132d3360301SVarun Wadekar { 133d3360301SVarun Wadekar tegra_gic_setup(NULL, 0); 134d3360301SVarun Wadekar } 135