1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <debug.h> 34 #include <mmio.h> 35 #include <platform.h> 36 #include <platform_def.h> 37 #include <psci.h> 38 #include <pmc.h> 39 #include <flowctrl.h> 40 #include <tegra_def.h> 41 #include <tegra_private.h> 42 43 /* 44 * Register used to clear CPU reset signals. Each CPU has two reset 45 * signals: CPU reset (3:0) and Core reset (19:16). 46 */ 47 #define CPU_CMPLX_RESET_CLR 0x454 48 #define CPU_CORE_RESET_MASK 0x10001 49 50 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 51 52 int32_t tegra_soc_validate_power_state(unsigned int power_state) 53 { 54 /* Sanity check the requested afflvl */ 55 if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { 56 /* 57 * It's possible to enter standby only on affinity level 0 i.e. 58 * a cpu on Tegra. Ignore any other affinity level. 59 */ 60 if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0) 61 return PSCI_E_INVALID_PARAMS; 62 } 63 64 /* Sanity check the requested state id */ 65 switch (psci_get_pstate_id(power_state)) { 66 case PSTATE_ID_CORE_POWERDN: 67 case PSTATE_ID_CLUSTER_IDLE: 68 case PSTATE_ID_CLUSTER_POWERDN: 69 case PSTATE_ID_SOC_POWERDN: 70 break; 71 72 default: 73 ERROR("unsupported state id\n"); 74 return PSCI_E_NOT_SUPPORTED; 75 } 76 77 return PSCI_E_SUCCESS; 78 } 79 80 int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl) 81 { 82 /* There's nothing to be done for affinity level 1 */ 83 if (afflvl == MPIDR_AFFLVL1) 84 return PSCI_E_SUCCESS; 85 86 switch (id) { 87 /* Prepare for cpu idle */ 88 case PSTATE_ID_CORE_POWERDN: 89 tegra_fc_cpu_idle(read_mpidr()); 90 return PSCI_E_SUCCESS; 91 92 /* Prepare for cluster idle */ 93 case PSTATE_ID_CLUSTER_IDLE: 94 tegra_fc_cluster_idle(read_mpidr()); 95 return PSCI_E_SUCCESS; 96 97 /* Prepare for cluster powerdn */ 98 case PSTATE_ID_CLUSTER_POWERDN: 99 tegra_fc_cluster_powerdn(read_mpidr()); 100 return PSCI_E_SUCCESS; 101 102 /* Prepare for system idle */ 103 case PSTATE_ID_SOC_POWERDN: 104 105 /* Enter system suspend state */ 106 tegra_pm_system_suspend_entry(); 107 108 /* suspend the entire soc */ 109 tegra_fc_soc_powerdn(read_mpidr()); 110 111 return PSCI_E_SUCCESS; 112 113 default: 114 ERROR("Unknown state id (%d)\n", id); 115 break; 116 } 117 118 return PSCI_E_NOT_SUPPORTED; 119 } 120 121 int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr) 122 { 123 /* 124 * Check if we are exiting from SOC_POWERDN. 125 */ 126 if (tegra_system_suspended()) { 127 128 /* 129 * Restore Boot and Power Management Processor (BPMP) reset 130 * address and reset it. 131 */ 132 tegra_fc_reset_bpmp(); 133 134 /* 135 * System resume complete. 136 */ 137 tegra_pm_system_suspend_exit(); 138 } 139 140 /* 141 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 142 * used for power management and boot purposes. Inform the BPMP that 143 * we have completed the cluster power up. 144 */ 145 if (psci_get_max_phys_off_afflvl() == MPIDR_AFFLVL1) 146 tegra_fc_lock_active_cluster(); 147 148 return PSCI_E_SUCCESS; 149 } 150 151 int tegra_soc_prepare_cpu_on(unsigned long mpidr) 152 { 153 int cpu = mpidr & MPIDR_CPU_MASK; 154 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 155 156 /* Deassert CPU reset signals */ 157 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 158 159 /* Turn on CPU using flow controller or PMC */ 160 if (cpu_powergate_mask[cpu] == 0) { 161 tegra_pmc_cpu_on(cpu); 162 cpu_powergate_mask[cpu] = 1; 163 } else { 164 tegra_fc_cpu_on(cpu); 165 } 166 167 return PSCI_E_SUCCESS; 168 } 169 170 int tegra_soc_prepare_cpu_off(unsigned long mpidr) 171 { 172 tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK); 173 return PSCI_E_SUCCESS; 174 } 175