1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <cortex_a57.h> 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <drivers/delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/psci/psci.h> 14 #include <plat/common/platform.h> 15 16 #include <bpmp.h> 17 #include <flowctrl.h> 18 #include <pmc.h> 19 #include <platform_def.h> 20 #include <security_engine.h> 21 #include <tegra_def.h> 22 #include <tegra_private.h> 23 #include <tegra_platform.h> 24 25 /* 26 * Register used to clear CPU reset signals. Each CPU has two reset 27 * signals: CPU reset (3:0) and Core reset (19:16). 28 */ 29 #define CPU_CMPLX_RESET_CLR 0x454 30 #define CPU_CORE_RESET_MASK 0x10001 31 32 /* Clock and Reset controller registers for system clock's settings */ 33 #define SCLK_RATE 0x30 34 #define SCLK_BURST_POLICY 0x28 35 #define SCLK_BURST_POLICY_DEFAULT 0x10000000 36 37 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; 38 39 int32_t tegra_soc_validate_power_state(unsigned int power_state, 40 psci_power_state_t *req_state) 41 { 42 int state_id = psci_get_pstate_id(power_state); 43 44 /* Sanity check the requested state id */ 45 switch (state_id) { 46 case PSTATE_ID_CORE_POWERDN: 47 /* 48 * Core powerdown request only for afflvl 0 49 */ 50 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; 51 52 break; 53 54 case PSTATE_ID_CLUSTER_IDLE: 55 case PSTATE_ID_CLUSTER_POWERDN: 56 /* 57 * Cluster powerdown/idle request only for afflvl 1 58 */ 59 req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; 60 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; 61 62 break; 63 64 case PSTATE_ID_SOC_POWERDN: 65 /* 66 * System powerdown request only for afflvl 2 67 */ 68 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 69 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 70 71 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = 72 PLAT_SYS_SUSPEND_STATE_ID; 73 74 break; 75 76 default: 77 ERROR("%s: unsupported state id (%d)\n", __func__, state_id); 78 return PSCI_E_INVALID_PARAMS; 79 } 80 81 return PSCI_E_SUCCESS; 82 } 83 84 /******************************************************************************* 85 * Platform handler to calculate the proper target power level at the 86 * specified affinity level 87 ******************************************************************************/ 88 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 89 const plat_local_state_t *states, 90 unsigned int ncpu) 91 { 92 plat_local_state_t target = PSCI_LOCAL_STATE_RUN; 93 int cpu = plat_my_core_pos(); 94 int core_pos = read_mpidr() & MPIDR_CPU_MASK; 95 uint32_t bpmp_reply, data[3]; 96 int ret; 97 98 /* get the power state at this level */ 99 if (lvl == MPIDR_AFFLVL1) 100 target = *(states + core_pos); 101 if (lvl == MPIDR_AFFLVL2) 102 target = *(states + cpu); 103 104 if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { 105 106 /* initialize the bpmp interface */ 107 (void)tegra_bpmp_init(); 108 109 /* Cluster idle */ 110 data[0] = (uint32_t)cpu; 111 data[1] = TEGRA_PM_CC6; 112 data[2] = TEGRA_PM_SC1; 113 ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, 114 (void *)&data, (int)sizeof(data), 115 (void *)&bpmp_reply, (int)sizeof(bpmp_reply)); 116 117 /* check if cluster idle entry is allowed */ 118 if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { 119 120 /* Cluster idle not allowed */ 121 target = PSCI_LOCAL_STATE_RUN; 122 } 123 124 } else if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_POWERDN)) { 125 126 /* initialize the bpmp interface */ 127 (void)tegra_bpmp_init(); 128 129 /* Cluster power-down */ 130 data[0] = (uint32_t)cpu; 131 data[1] = TEGRA_PM_CC7; 132 data[2] = TEGRA_PM_SC1; 133 ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, 134 (void *)&data, (int)sizeof(data), 135 (void *)&bpmp_reply, (int)sizeof(bpmp_reply)); 136 137 /* check if cluster power down is allowed */ 138 if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { 139 140 /* Cluster power down not allowed */ 141 target = PSCI_LOCAL_STATE_RUN; 142 } 143 144 } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && 145 (target == PSTATE_ID_SOC_POWERDN)) { 146 147 /* System Suspend */ 148 target = PSTATE_ID_SOC_POWERDN; 149 150 } else { 151 ; /* do nothing */ 152 } 153 154 return target; 155 } 156 157 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 158 { 159 u_register_t mpidr = read_mpidr(); 160 const plat_local_state_t *pwr_domain_state = 161 target_state->pwr_domain_state; 162 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; 163 unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; 164 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; 165 int ret = PSCI_E_SUCCESS; 166 167 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 168 169 assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || 170 (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); 171 assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || 172 (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); 173 174 if (tegra_chipid_is_t210_b01()) { 175 176 /* Suspend se/se2 and pka1 */ 177 if (tegra_se_suspend() != 0) { 178 ret = PSCI_E_INTERN_FAIL; 179 } 180 } 181 182 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { 183 184 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); 185 186 /* Prepare for cluster idle */ 187 tegra_fc_cluster_idle(mpidr); 188 189 } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) { 190 191 assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); 192 193 /* Prepare for cluster powerdn */ 194 tegra_fc_cluster_powerdn(mpidr); 195 196 } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { 197 198 /* Prepare for cpu powerdn */ 199 tegra_fc_cpu_powerdn(mpidr); 200 201 } else { 202 ERROR("%s: Unknown state id (%d, %d, %d)\n", __func__, 203 stateid_afflvl2, stateid_afflvl1, stateid_afflvl0); 204 ret = PSCI_E_NOT_SUPPORTED; 205 } 206 207 return ret; 208 } 209 210 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 211 { 212 u_register_t mpidr = read_mpidr(); 213 const plat_local_state_t *pwr_domain_state = 214 target_state->pwr_domain_state; 215 unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL]; 216 217 if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { 218 219 if (tegra_chipid_is_t210_b01()) { 220 /* Save tzram contents */ 221 tegra_se_save_tzram(); 222 } 223 224 /* enter system suspend */ 225 tegra_fc_soc_powerdn(mpidr); 226 } 227 228 return PSCI_E_SUCCESS; 229 } 230 231 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 232 { 233 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); 234 uint32_t val; 235 236 /* platform parameter passed by the previous bootloader */ 237 if (plat_params->l2_ecc_parity_prot_dis != 1) { 238 /* Enable ECC Parity Protection for Cortex-A57 CPUs */ 239 val = read_l2ctlr_el1(); 240 val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 241 write_l2ctlr_el1(val); 242 } 243 244 /* 245 * Check if we are exiting from SOC_POWERDN. 246 */ 247 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 248 PLAT_SYS_SUSPEND_STATE_ID) { 249 250 /* 251 * Security engine resume 252 */ 253 if (tegra_chipid_is_t210_b01()) { 254 tegra_se_resume(); 255 } 256 257 /* 258 * Lock scratch registers which hold the CPU vectors 259 */ 260 tegra_pmc_lock_cpu_vectors(); 261 262 /* 263 * Enable WRAP to INCR burst type conversions for 264 * incoming requests on the AXI slave ports. 265 */ 266 val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); 267 val &= ~ENABLE_UNSUP_TX_ERRORS; 268 val |= ENABLE_WRAP_TO_INCR_BURSTS; 269 mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); 270 271 /* 272 * Restore Boot and Power Management Processor (BPMP) reset 273 * address and reset it. 274 */ 275 tegra_fc_reset_bpmp(); 276 } 277 278 /* 279 * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's 280 * used for power management and boot purposes. Inform the BPMP that 281 * we have completed the cluster power up. 282 */ 283 tegra_fc_lock_active_cluster(); 284 285 return PSCI_E_SUCCESS; 286 } 287 288 int tegra_soc_pwr_domain_on(u_register_t mpidr) 289 { 290 int cpu = mpidr & MPIDR_CPU_MASK; 291 uint32_t mask = CPU_CORE_RESET_MASK << cpu; 292 293 /* Deassert CPU reset signals */ 294 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); 295 296 /* Turn on CPU using flow controller or PMC */ 297 if (cpu_powergate_mask[cpu] == 0) { 298 tegra_pmc_cpu_on(cpu); 299 cpu_powergate_mask[cpu] = 1; 300 } else { 301 tegra_fc_cpu_on(cpu); 302 } 303 304 return PSCI_E_SUCCESS; 305 } 306 307 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 308 { 309 tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); 310 return PSCI_E_SUCCESS; 311 } 312 313 int tegra_soc_prepare_system_reset(void) 314 { 315 /* 316 * Set System Clock (SCLK) to POR default so that the clock source 317 * for the PMC APB clock would not be changed due to system reset. 318 */ 319 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, 320 SCLK_BURST_POLICY_DEFAULT); 321 mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); 322 323 /* Wait 1 ms to make sure clock source/device logic is stabilized. */ 324 mdelay(1); 325 326 return PSCI_E_SUCCESS; 327 } 328